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    Memories having select devices between access lines and in memory cells formed of a same type of circuit element
    33.
    发明授权
    Memories having select devices between access lines and in memory cells formed of a same type of circuit element 有权

    公开(公告)号：US10049705B2

    公开(公告)日：2018-08-14

    申请号：US15656690

    申请日：2017-07-21

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Aaron Yip

    IPC: G11C5/06 ,  G11C7/18 ,  G11C13/00

    Abstract: Memories may include a first select device connected between a first access line and a second access line, and a plurality of memory cells. Each memory cell of the plurality of memory cells may be connected between the second access line and a respective third access line of a plurality of third access lines. Each memory cell of the plurality of memory cells may include a respective second select device, of a plurality of second select devices, and a respective programmable element, of a plurality of programmable elements, connected in series, and the first select device and each second select device of the plurality of second select devices may each be formed of a same type of circuit element.

    APPARATUSES AND METHODS USING DUMMY CELLS PROGRAMMED TO DIFFERENT STATES
    37.
    发明申请
    APPARATUSES AND METHODS USING DUMMY CELLS PROGRAMMED TO DIFFERENT STATES 有权
    使用编程到不同状态的细胞的装置和方法

    公开(公告)号：US20160343446A1

    公开(公告)日：2016-11-24

    申请号：US15227623

    申请日：2016-08-03

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Toru Tanzawa ,  Aaron Yip

    IPC: G11C16/28 ,  G11C16/08 ,  G11C16/24 ,  G11C16/04

    CPC classification number: G11C16/28 ,  G11C7/02 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24 ,  G11C16/3427

    Abstract: Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.

    Abstract translation: 描述了用于降低电容负载的装置和方法。 一种装置包括包括第一和第二虚拟存储器单元的第一存储器串，包括第三和第四伪存储单元的第二存储器串，以及控制单元，被配置为提供第一和第二控制信号，以激活第一和第二虚拟存储单元 并且进一步去激活第二存储器串的第三和第四伪存储单元中的至少一个。

    Semiconductor devices including stair step structures, and related methods
    38.
    发明授权
    Semiconductor devices including stair step structures, and related methods 有权
    半导体器件包括楼梯台阶结构及相关方法

    公开(公告)号：US09165937B2

    公开(公告)日：2015-10-20

    申请号：US13932551

    申请日：2013-07-01

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip ,  Qiang Tang ,  Chang Wan Ha

    IPC: H01L27/115

    CPC classification number: H01L27/11556 ,  G11C16/06 ,  H01L27/115 ,  H01L27/11565 ,  H01L27/1157 ,  H01L27/11575 ,  H01L27/11582

    Abstract: Semiconductor devices, such as three-dimensional memory devices, include a memory array including a stack of conductive tiers and a stair step structure. The stair step structure is positioned between first and second portions of the memory array and includes contact regions for respective conductive tiers of the stack of conductive tiers. The first portion of the memory array includes a first plurality of select gates extending in a particular direction over the stack. The second portion of the memory array includes a second plurality of select gates also extending in the particular direction over the stack of conductive tiers. Methods of forming and methods of operating such semiconductor devices, including vertical memory devices, are also disclosed.

    Abstract translation: 诸如三维存储器件的半导体器件包括包括导电层堆叠和阶梯结构的存储器阵列。 阶梯结构位于存储器阵列的第一和第二部分之间，并且包括用于导电层叠层的相应导电层的接触区域。 存储器阵列的第一部分包括在堆叠上沿特定方向延伸的第一多个选择栅极。 存储器阵列的第二部分包括第二多个选择栅极，其也沿着导电层叠层的特定方向延伸。 还公开了形成方法和操作这种半导体器件的方法，包括垂直存储器件。

    Select gate programming in a memory device
    39.
    发明授权
    Select gate programming in a memory device 有权
    在存储设备中选择门编程

    公开(公告)号：US08873297B2

    公开(公告)日：2014-10-28

    申请号：US14018926

    申请日：2013-09-05

    Applicant: Micron Technology, Inc.

    Inventor： Shigekazu Yamada ,  Aaron Yip

    IPC: G11C11/34 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/34

    CPC classification number: G11C16/102 ,  G11C16/0483 ,  G11C16/24 ,  G11C16/3427

    Abstract: Methods for programming select gates, memory devices, and memory systems are disclosed. In one such method for programming, a program inhibit voltage is transferred from a source to unselected bit lines. Bit line-to-bit line capacitance, between the unselected bit lines and selected bit lines to be program inhibited, boosts the bit line voltage of the selected, inhibited bit lines to a target inhibit voltage. In one embodiment, the voltage on the selected, inhibited bit line can be increased in a plurality of inhibit steps whereby either one, two, or all of the steps can be used during the programming of unprogrammed select gates.

    Abstract translation: 公开了用于编程选择门，存储器件和存储器系统的方法。 在一种用于编程的方法中，程序禁止电压从源传输到未选位线。 在未被选择的位线和要被编程禁止的选定位线之间的位线对位线电容将所选择的禁止位线的位线电压升高到目标抑制电压。 在一个实施例中，可以在多个禁止步骤中增加所选择的禁止位线上的电压，由此在编程的未选择栅极的编程期间可以使用一个，两个或所有步骤。

    Multi-pass programming in a memory device
    40.
    发明授权
    Multi-pass programming in a memory device 有权
    在存储设备中进行多遍编程

    公开(公告)号：US08547749B2

    公开(公告)日：2013-10-01

    申请号：US13775523

    申请日：2013-02-25

    Applicant: Micron Technology, Inc.

    Inventor： Aaron Yip

    IPC: G11C11/34

    CPC classification number: G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/3454 ,  G11C16/3459 ,  G11C2211/5621

    Abstract: A method for programming a memory device, a memory device, and a memory system are provided. According to at least one such method, a first programming pass generates a plurality of first programming pulses to increase the threshold voltages of target memory cells to either a pre-program level or to the highest programmed threshold. A second programming pass applies a plurality of second programming pulses to the target memory cells to increase their threshold voltages only if they were programmed to the pre-program level. The target memory cells programmed to their respective target threshold levels during the first pass are not programmed further.

    Abstract translation: 提供了一种用于对存储器件，存储器件和存储器系统进行编程的方法。 根据至少一种这样的方法，第一编程通道产生多个第一编程脉冲，以将目标存储器单元的阈值电压增加到预编程级或最高编程阈值。 第二编程通道将多个第二编程脉冲施加到目标存储器单元，以便仅当它们被编程为预编程级时才增加它们的阈值电压。 在第一次通过期间被编程到它们各自的目标阈值水平的目标存储器单元没有进一步编程。

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