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    MULTIPLE PLATE LINE ARCHITECTURE FOR MULTIDECK MEMORY ARRAY
    31.
    发明申请
    MULTIPLE PLATE LINE ARCHITECTURE FOR MULTIDECK MEMORY ARRAY 审中-公开

    公开(公告)号：US20190244652A1

    公开(公告)日：2019-08-08

    申请号：US16387208

    申请日：2019-04-17

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi

    IPC: G11C11/22 ,  H01L27/11502 ,  H01L27/11514

    Abstract: Methods, systems, and devices for multiple plate line architecture for multideck memory arrays are described. A memory device may include two or more three-dimensional arrays of ferroelectric memory cells overlying a substrate layer that includes various components of support circuitry, such as decoders and sense amplifiers. Each memory cell of the array may have a ferroelectric container and a selector device. Multiple plate lines or other access lines may be routed through the various decks of the device to support access to memory cells within those decks. Plate lines or other access lines may be coupled between support circuitry and memory cells through on pitch via (OPV) structures. OPV structures may include selector devices to provide an additional degree of freedom in multideck selectivity. Various number of plate lines and access lines may be employed to accommodate different configurations and orientations of the ferroelectric containers.

    Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator
    32.
    发明授权
    Memory cells comprising a programmable field effect transistor having a reversibly programmable gate insulator 有权

    公开(公告)号：US10332910B2

    公开(公告)日：2019-06-25

    申请号：US15944270

    申请日：2018-04-03

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi

    IPC: G11C15/02 ,  H01L27/11597 ,  H01L29/78 ,  H01L27/1159 ,  H01L27/11587 ,  H01L29/423 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A memory cell comprises an elevationally extending programmable field effect transistor comprising a gate insulator that is reversibly programmable into two programmable states characterized by two different Vt's of the programmable transistor. The programmable transistor comprises a top source/drain region and a bottom source/drain region. A bottom select device is electrically coupled in series with and elevationally inward of the bottom source/drain region of the programmable transistor. A top select device is electrically coupled in series with and is elevationally outward of the top source/drain region of the programmable transistor. A bottom select line is electrically coupled in series with and is elevationally inward of the bottom select device. A top select line is electrically coupled in series with and is elevationally outward of the top select device. Other embodiments are disclosed.

    VARIABLE FILTER CAPACITANCE
    35.
    发明申请
    VARIABLE FILTER CAPACITANCE 审中-公开

    公开(公告)号：US20190035441A1

    公开(公告)日：2019-01-31

    申请号：US16020834

    申请日：2018-06-27

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

    IPC: G11C7/14 ,  G11C11/24 ,  G11C11/22 ,  G11C11/408

    CPC classification number: G11C7/14 ,  G11C5/063 ,  G11C5/147 ,  G11C8/08 ,  G11C8/14 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2297 ,  G11C11/24 ,  G11C11/408

    Abstract: Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array.

    COMPENSATING FOR VARIATIONS IN SELECTOR THRESHOLD VOLTAGES
    37.
    发明申请
    COMPENSATING FOR VARIATIONS IN SELECTOR THRESHOLD VOLTAGES 有权

    公开(公告)号：US20180102157A1

    公开(公告)日：2018-04-12

    申请号：US15291711

    申请日：2016-10-12

    Applicant: Micron Technology, Inc.

    Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

    IPC: G11C11/22

    CPC classification number: G11C11/2259 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2277 ,  G11C11/2293

    Abstract: Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of the memory cell prior to applying a second voltage to the memory cell. The second voltage may be applied to facilitate a sensing operation once the selection component is activated. The first voltage may be applied during a first portion of an access operation and may be used in determining a threshold voltage of the selection component. The subsequently applied second voltage may be applied during a second portion of the access operation and may have a magnitude associated with a preferred voltage for accessing a ferroelectric capacitor of the memory cell. In some cases, the second voltage has a greater rate of increase over time (e.g., a greater “ramp”) than the first voltage.

    FULL BIAS SENSING IN A MEMORY ARRAY
    38.
    发明申请
    FULL BIAS SENSING IN A MEMORY ARRAY 审中-公开

    公开(公告)号：US20180061470A1

    公开(公告)日：2018-03-01

    申请号：US15246249

    申请日：2016-08-24

    Applicant: Micron Technology, Inc.

    Inventor： Umberto Di Vincenzo ,  Ferdinando Bedeschi

    IPC: G11C11/22

    CPC classification number: G11C11/2273 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2275

    Abstract: Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

    SENSE CIRCUITS, MEMORY DEVICES, AND RELATED METHODS FOR RESISTANCE VARIABLE MEMORY
    40.
    发明申请
    SENSE CIRCUITS, MEMORY DEVICES, AND RELATED METHODS FOR RESISTANCE VARIABLE MEMORY 有权
    感知电路，存储器件和相关的电阻可变存储器的方法

    公开(公告)号：US20170040045A1

    公开(公告)日：2017-02-09

    申请号：US15258204

    申请日：2016-09-07

    Applicant: Micron Technology, Inc.

    Inventor： Michele Piccardi ,  Ferdinando Bedeschi

    IPC: G11C11/16

    CPC classification number: G11C11/1673 ,  G11C7/06 ,  G11C11/161 ,  G11C11/1693 ,  G11C11/5607 ,  G11C13/0002 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0047 ,  G11C2013/0057

    Abstract: Sense circuits, memory devices, and related methods are disclosed. A sense circuit includes sample and hold circuitry configured to sample and hold a second response voltage potential, a first response voltage potential, and a third response voltage potential responsive to an evaluation signal applied to a resistance variable memory cell. The sense circuit includes an amplifier operably coupled to the sample and hold circuitry. The amplifier is configured to amplify a difference between a sum of the first response voltage potential and the third response voltage potential, and twice the second response voltage potential. A memory device includes an evaluation signal generating circuit configured to provide the evaluation signal, an array of resistance variable memory cells, and the sense circuit. A method includes applying the evaluation signal to the resistance variable memory cell, sampling and holding the response voltage potentials, and discharging the sample and hold circuitry to the amplifier.

    Abstract translation: 感测电路，存储器件和相关方法被公开。 感测电路包括采样和保持电路，其被配置为响应于施加到电阻变量存储单元的评估信号来采样和保持第二响应电压电位，第一响应电压电位和第三响应电压电位。 感测电路包括可操作地耦合到采样和保持电路的放大器。 放大器被配置为放大第一响应电压电位和第三响应电压电位之和与第二响应电压电位的两倍之间的差。 存储器件包括：评估信号发生电路，被配置为提供评估信号，电阻可变存储单元阵列和感测电路。 一种方法包括将评估信号施加到电阻可变存储单元，采样并保持响应电压电位，并将取样和保持电路放电到放大器。

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