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公开(公告)号：US11915785B2
公开(公告)日：2024-02-27
申请号：US17415657
申请日：2021-01-26
发明人： Jiangang Wu , Lei Zhou , Jung Sheng Hoei , Kishore Kumar Muchherla , Qisong Lin
CPC分类号： G11C7/1096 , G11C8/08 , G11C8/14 , G11C16/10
摘要： A request to perform a write operation at a memory device is received. Current wordline start voltage (WLSV) information associated with a particular memory segment of the plurality of memory segments is retrieved. The write operation is performed on the particular memory segment. In a firmware record in a memory sub-system controller, information is stored indicative of a last written memory page associated with the particular memory segment on which the write operation is performed. The firmware record is managed in view of the information indicative of the last written memory page associated with the performed write operation. Each entry of the firmware record comprises one or more identifying indicia associated with a respective memory segment, at least one of the identifying indicia being a wordline start voltage (WLSV) associated with the respective memory segment.
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公开(公告)号：US11749362B2
公开(公告)日：2023-09-05
申请号：US17726112
申请日：2022-04-21
CPC分类号： G11C16/349 , G11C16/16 , G11C16/26 , G11C16/3404 , G11C16/3477
摘要： A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.
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公开(公告)号：US11615029B2
公开(公告)日：2023-03-28
申请号：US16730881
申请日：2019-12-30
发明人： Jiangang Wu , Qisong Lin , Jung Sheng Hoei , Yunqiu Wan , Ashutosh Malshe , Peng-Cheng Chen
IPC分类号： G06F11/00 , G06F12/0891 , G06F12/0811 , G06F12/02 , G06F12/0882 , G06F11/14 , G11C16/06 , G06F13/16
摘要： Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.
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公开(公告)号：US20230017388A1
公开(公告)日：2023-01-19
申请号：US17873850
申请日：2022-07-26
发明人： Qisong Lin , Shuai Xu , Jonathan S. Parry , Jeremy Binfet , Micheie Piccardi , Qing Liang
IPC分类号： G11C16/30 , G06F3/06 , G06F12/0875 , G11C16/10
摘要： Methods, systems, and devices for power architecture for non-volatile memory are described. A memory device may be configured to operate in a first mode and a second mode (e.g., a low power mode). When operating in the first mode, a voltage may be supplied from a power source (e.g., a power management integrated circuit) to a memory array and one or more associated components via a regulator. When the memory device transitions to operate in the second mode, some of the components supplied from the power source may be powered by a charge pump. Control information associated with the memory array may be stored to the one or more components (e.g., to a cache) that are powered by a charge pump.
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公开(公告)号：US11348650B2
公开(公告)日：2022-05-31
申请号：US16928799
申请日：2020-07-14
摘要： A failed erase operation is detected at a memory block of a memory device. Based on detecting the failed erase operation at the memory block, data on the memory block is destroyed using a data destruction algorithm that corrupts data stored by one or more cells of the block. The data on the memory block is verified to be destroyed. A passing data destruction status for the memory block is provided based on verifying the data on the memory block is destroyed.
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公开(公告)号：US20210389949A1
公开(公告)日：2021-12-16
申请号：US16902009
申请日：2020-06-15
摘要： Disclosed in some examples are methods, systems, devices, memory controllers, memory dies, memory devices, and machine-readable mediums that allow for efficient updating of software instructions of the memory die. In some examples, the controller of the memory device may cause the software instructions of one or more memory dies to be updated by causing the page buffers of the one or more memory dies to be loaded with updated software instructions and subsequently issuing a command to the memory die to update the software instructions from the page buffer.
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公开(公告)号：US11163488B2
公开(公告)日：2021-11-02
申请号：US16041649
申请日：2018-07-20
发明人： Vamsi Pavan Rayaprolu , Sampath K. Ratnam , Sivagnanam Parthasarathy , Mustafa N. Kaynak , Kishore Kumar Muchherla , Shane Nowell , Peter Feeley , Qisong Lin
摘要： An indication of a programming temperature at which data is written at a first location of the memory component is received. If it is indicated that the programming temperature is outside of a temperature range associated with the memory component, the data written to the first location of the memory component is re-written to a second location of the memory component when an operating temperature of the memory component returns within the temperature range.
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公开(公告)号：US20210200682A1
公开(公告)日：2021-07-01
申请号：US16730881
申请日：2019-12-30
发明人： Jiangang Wu , Qisong Lin , Jung Sheng Hoei , Yunqiu Wan , Ashutosh Malshe , Peng-Cheng Chen
IPC分类号： G06F12/0891 , G06F12/0882 , G06F12/02 , G06F12/0811
摘要： Methods, systems, and devices for full multi-plane operation enablement are described. A flash controller can determine that a first plane of a set of planes of a memory die is an invalid plane. The flash controller can issue a single descriptor associated with a multi-plane operation for the set of planes of the memory die. The single descriptor can include a plurality of commands for the multi-plane operation in which the first command of the plurality of commands can be a duplicate of a second command of the plurality of commands based on the first plane being the invalid plane. In some cases, a negative-and (NAND) controller can receive the single descriptor associated with the multi-plane operation for the set of planes of a memory die. The NAND controller can issue a plurality of commands for the multi-plane operation based on receiving the single descriptor.
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公开(公告)号：US20210165703A1
公开(公告)日：2021-06-03
申请号：US16702399
申请日：2019-12-03
发明人： Vamsi Pavan Rayaprolu , Harish R. Singidi , Ashutosh Malshe , Sampath K. Ratnam , Qisong Lin , Kishore Kumar Muchherla
摘要： Read operations can be performed to read data stored at a data block. Parameters reflective of a separation between a pair of programming distributions associated with the data block can be determined based on the plurality of read operations. A read request to read the data stored at the data block can be received. In response to receiving the read request, a read operation can be performed to read the data stored at the data block based on the parameters that are reflective of the separation between the pair of programming distributions associated with the data block.
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40.发明申请公开(公告)号：US20190250843A1
公开(公告)日：2019-08-15
申请号：US16100681
申请日：2018-08-10
发明人： Sampath K. Ratnam , Vamsi Pavan Rayaprolu , Mustafa N. Kaynak , Sivagnanam Parthasarathy , Kishore Kumar Muchherla , Shane Nowell , Peter Feeley , Qisong Lin
CPC分类号： G06F3/0647 , G06F3/0619 , G06F3/0673 , G06F11/1068 , G11C29/52
摘要： At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.
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