公开(公告)号：US20100030421A1

公开(公告)日：2010-02-04

申请号：US12575212

申请日：2009-10-07

申请人： Kentaro YOSHIMURA ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Yuichiro Morita ,  Yoshiaki Takahashi ,  Kenichi Kurosawa ,  Toshimichi Minowa ,  Masatoshi Hoshino ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Kunihiko Tsunedomi ,  Shoji Sasaki

发明人： Kentaro YOSHIMURA ,  Kohei Sakurai ,  Nobuyasu Kanekawa ,  Yuichiro Morita ,  Yoshiaki Takahashi ,  Kenichi Kurosawa ,  Toshimichi Minowa ,  Masatoshi Hoshino ,  Yasuhiro Nakatsuka ,  Kotaro Shimamura ,  Kunihiko Tsunedomi ,  Shoji Sasaki

IPC分类号： B60W10/00

CPC分类号： B60W30/00 ,  B60K6/46 ,  B60K6/52 ,  B60L3/0023 ,  B60L3/003 ,  B60L3/0076 ,  B60L3/0092 ,  B60L15/2009 ,  B60L2240/12 ,  B60L2240/20 ,  B60L2240/24 ,  B60L2240/423 ,  B60L2250/26 ,  B60T7/12 ,  B60W10/04 ,  B60W10/06 ,  B60W10/08 ,  B60W10/10 ,  B60W10/18 ,  B60W10/20 ,  B60W20/00 ,  B60W40/08 ,  B60W40/10 ,  B60W50/02 ,  B60W50/0225 ,  B60W50/04 ,  B60W2510/20 ,  B60W2510/202 ,  B60W2520/14 ,  B60W2540/10 ,  B60W2540/12 ,  B60W2550/20 ,  B62D5/046 ,  B62D5/0481 ,  B62D6/00 ,  G06F11/0796 ,  Y02T10/6217 ,  Y02T10/6265 ,  Y02T10/6286 ,  Y02T10/645 ,  Y02T10/72 ,  Y02T10/7275 ,  Y02T90/16

摘要： A vehicle control system which can ensure high reliability, real-time processing, and expandability with a simplified ECU configuration and a low cost by backing up an error through coordination in the entire system without increasing a degree of redundancy of individual controllers beyond the least necessary level. The vehicle control system comprises a sensor controller for taking in sensor signals indicating a status variable of a vehicle and an operation amount applied from a driver, a command controller for generating a control target value based on the sensor signals taken in by the sensor controller, and an actuator controller for receiving the control target value from the command controller and operating an actuator to control the vehicle, those three controller being interconnected via a network. The actuator controller includes a control target value generating unit for generating a control target value based on the sensor signals taken in by the sensor controller and received by the actuator controller via the network when the control target value generated by the command controller is abnormal, and controls the actuator in accordance with the control target value generated by the control target value generating unit.

摘要翻译： 一种车辆控制系统，可以通过简化的ECU配置和低成本确保高可靠性，实时处理和可扩展性，通过整个系统中的协调备份错误，而不会增加单个控制器的冗余程度，超出最不必要的范围 水平。 车辆控制系统包括：传感器控制器，用于接收指示车辆的状态变量的传感器信号和从驾驶员施加的操作量;命令控制器，用于基于由传感器控制器接收的传感器信号产生控制目标值; 以及致动器控制器，用于从命令控制器接收控制目标值并操作致动器来控制车辆，这三个控制器经由网络互连。 执行器控制器包括控制目标值产生单元，用于当由指令控制器产生的控制目标值异常时，基于由传感器控制器接收并由致动器控制器经由网络接收的传感器信号产生控制目标值;以及 根据由控制目标值产生单元产生的控制目标值来控制致动器。

公开(公告)号：US06289407B1

公开(公告)日：2001-09-11

申请号：US09499897

申请日：2000-02-08

申请人： Tsutomu Yamada ,  Kenichi Kurosawa ,  Yasuo Kaminaga ,  Kouji Masui ,  Akihiro Ohashi

发明人： Tsutomu Yamada ,  Kenichi Kurosawa ,  Yasuo Kaminaga ,  Kouji Masui ,  Akihiro Ohashi

IPC分类号： G06F1300

CPC分类号： G06F13/4081 ,  G06F1/189 ,  Y02D10/14 ,  Y02D10/151

摘要： There is provided an input/output device having of not exerting any adverse influence on other expansion devices connected to a system bus at the time of insertion or removal. An expansion device 800 comprises an electronic circuit 400 and a MOS switch 300, and is connected to a system bus (BUS) via a connector having long and short pins. The expansion device 800 two power supply systems, namely a stable power supply 250 and an unstable power supply 260. At the time of insertion or removal of the expansion device 800, power is provided to the MOS switch 300 and a high impedance maintaining circuit from the stable power supply via a pair of long pins, so as to reliably place the MOS switch 300 in a high impedance state, inside the expansion device the high impedance maintaining circuit 350 drives an open/close control terminal, and power is provided to the electronic circuit 400 from the unstable power supply 260. At the time of insertion or removal, adverse influence is not exerted on the signal transmission on the system bus, and effects of load variation on the main power supply are reduced.

摘要翻译： 提供了一种输入/输出装置，其在插入或移除时对连接到系统总线的其它扩展装置没有任何不利影响。 扩展装置800包括电子电路400和MOS开关300，并且经由具有长和短引脚的连接器连接到系统总线（BUS）。 膨胀装置800是两个电源系统，即稳定的电源250和不稳定的电源260.在插入或移除扩展装置800时，向MOS开关300提供电力和高阻抗保持电路 通过一对长引脚稳定供电，为了可靠地将MOS开关300置于高阻抗状态，高阻抗保持电路350在扩展装置的内部驱动开/关控制端子，并且向 来自不稳定电源260的电子电路400.在插入或移除时，不会对系统总线上的信号传输产生不利影响，并且降低对主电源的负载变化的影响。

公开(公告)号：US06249363B1

公开(公告)日：2001-06-19

申请号：US09115763

申请日：1998-07-15

申请人： Hiroshi Arita ,  Tetsuaki Nakamikawa ,  Kenichi Kurosawa ,  Hiroaki Fukumaru ,  Hisao Ogawa

发明人： Hiroshi Arita ,  Tetsuaki Nakamikawa ,  Kenichi Kurosawa ,  Hiroaki Fukumaru ,  Hisao Ogawa

IPC分类号： H04B1020

CPC分类号： H04B10/271 ,  G06F13/4022 ,  H04B10/27 ,  H04B10/278

摘要： The system includes optical bus-bridging devices for observing the modes of said electric buses and the modes of said optical fibers while said electric buses have not been driven (OFF mode), so that the modes of the two electric buses connected through optical fibers are brought into agreement and that the buses can be simultaneously driven by a plurality of nodes. While one or both of said electric buses have been driven (ON mode) by the nodes connected thereto, an optical output has been continuously produced from the buses that are being driven to said optical fibers, and while light has been inputted from said optical fibers, the modes of said buses are not observed, but an electric output is produced to the electric bus of the side to which light is inputted to drive the bus. The optical bus-bridging device changes the mode of the electric bus when the optical fiber does not change within a predetermined period of time after the optical bus-bridging device has outputted a signal to the optical fiber.

摘要翻译： 该系统包括用于在所述电气总线未被驱动（OFF模式）下观察所述电动总线的模式和所述光纤的模式的光学总线桥接装置，使得通过光纤连接的两条电动总线的模式为 使总线同时由多个节点驱动。 虽然所述电气总线中的一个或两个已经被连接到其上的节点驱动（ON模式），但是已经从被驱动到所述光纤的总线连续地产生光输出，并且在从所述光纤输入光 没有观察到所述总线的模式，而是向输入光的一侧的电力总线产生电力输出以驱动总线。 光总线桥接装置在光总线桥接装置向光纤输出信号之后光纤在预定时间内不变化时，改变电气总线的模式。

公开(公告)号：US5784630A

公开(公告)日：1998-07-21

申请号：US367928

申请日：1995-01-03

申请人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

发明人： Masahiko Saito ,  Kenichi Kurosawa ,  Yoshiki Kobayashi ,  Tadaaki Bandoh ,  Masahiro Iwamura ,  Takashi Hotta ,  Yasuhiro Nakatsuka ,  Shigeya Tanaka ,  Takeshi Takemoto

IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/173 ,  G06F15/80

CPC分类号： G06F9/3891 ,  G06F12/084 ,  G06F15/17381 ,  G06F15/8015 ,  G06F9/30087 ,  G06F9/3009 ,  G06F9/30181 ,  G06F9/3802 ,  G06F9/3814 ,  G06F9/3822 ,  G06F9/3824 ,  G06F9/3836 ,  G06F9/3851 ,  G06F9/3885

摘要： A data processing system having flexibility coping with parallelism of a program comprises a plurality of processor elements for executing instructions, a main memory shared by the plurality of processor elements, and a plurality of parallel operation control facilities for enabling the plurality of processor elements to operate in synchronism. The plurality of parallel operation control facilities are provided in correspondence to the plurality of processor elements, respectively. The data processing system further comprises a multiprocessor operation control facility for enabling the plurality of processor elements to operate independently, and a flag for holding a value indicating which of the parallel operation mode or the multiprocessor mode is to be activated. The shared cache memory is implemented in a blank instruction and controlled by a cache controller so that inconsistency of the data stored in the cache memory is eliminated.

公开(公告)号：US5748873A

公开(公告)日：1998-05-05

申请号：US686486

申请日：1996-07-26

申请人： Hiroshi Ohguro ,  Koichi Ikeda ,  Takaaki Nishiyama ,  Hiroshi Iwamoto ,  Kenichi Kurosawa ,  Tetsuaki Nakamikawa ,  Michio Morioka

发明人： Hiroshi Ohguro ,  Koichi Ikeda ,  Takaaki Nishiyama ,  Hiroshi Iwamoto ,  Kenichi Kurosawa ,  Tetsuaki Nakamikawa ,  Michio Morioka

IPC分类号： G06F11/16 ,  G06F11/34

CPC分类号： G06F11/165 ,  G06F11/1658 ,  G06F11/1679

摘要： A highly reliable computer system is intended to duplicate processors, compare the outputs of the processors with each other and enhance the validity of the output of processor system. If a mismatch between the outputs is detected, one of the processors performs a process of saving an internal state of the processor in amain memory and diagnosing factor of the detected mismatch. If the process is recognized to be continued in a duplex mode, the processors are re-synchronized by a processor reset, and initialize themselves and restore the internal information saved in the main memory for continuing the process having been proceeded before the fault occurred.

摘要翻译： 高度可靠的计算机系统旨在复制处理器，将处理器的输出相互比较，并提高处理器系统输出的有效性。 如果检测到输出之间的不匹配，则其中一个处理器执行将处理器的内部状态保存在大量存储器中并诊断检测到的失配的因素的处理。 如果该处理被识别为以双工模式继续，则处理器通过处理器复位重新同步，并且自己初始化并恢复保存在主存储器中的内部信息，以便继续在故障发生之前进行的处理。

公开(公告)号：US5699541A

公开(公告)日：1997-12-16

申请号：US406147

申请日：1995-03-20

申请人： Kenichi Kurosawa ,  Shin Kokura ,  Michio Morioka ,  Tetsuaki Nakamikawa ,  Sakou Ishikawa

发明人： Kenichi Kurosawa ,  Shin Kokura ,  Michio Morioka ,  Tetsuaki Nakamikawa ,  Sakou Ishikawa

IPC分类号： G11C11/417 ,  G06F13/16 ,  G11C7/10 ,  G11C11/409 ,  G06F12/00 ,  G06F9/26 ,  G06F9/32 ,  G06F12/02

CPC分类号： G11C7/1051 ,  G11C7/1078

摘要： A computer memory system is disclosed with an input/output circuitry capable of separating the load separating the load capacitance of an output circuit of a semiconductor memory connected to a memory bus from the memory bus. In order to separate the load capacitance of a semiconductor memory connected to a memory bus signal line, a Schottky diode is arranged between the semiconductor memory and the memory bus line, and a voltage control circuit is provided to control whether a reverse bias voltage is applied to the Schottky diode. The speed of signal transmission does not decrease even when a large number of semiconductor memories are connected to the memory bus since the load capacitance of the semiconductor memories is separated from the bus. Therefore, it is possible to construct a high speed and large capacity memory system.

摘要翻译： 公开了具有输入/输出电路的计算机存储器系统，该输入/输出电路能够将连接到存储器总线的半导体存储器的输出电路的负载电容与存储器总线分开。 为了分离连接到存储器总线信号线的半导体存储器的负载电容，在半导体存储器和存储器总线之间布置肖特基二极管，并且提供电压控制电路以控制是否施加反向偏置电压 到肖特基二极管。 即使当半导体存储器的负载电容与总线分离时，即使大量的半导体存储器连接到存储器总线，信号传输的速度也不会降低。 因此，可以构建高速，大容量的存储系统。

公开(公告)号：US5561775A

公开(公告)日：1996-10-01

申请号：US360081

申请日：1994-12-20

申请人： Kenichi Kurosawa ,  Shigeya Tanaka ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh

发明人： Kenichi Kurosawa ,  Shigeya Tanaka ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/177 ,  G06F9/445

CPC分类号： G06F9/30189 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

摘要： A parallel processing apparatus which includes a program counter for indicating instructions to be read out from a memory, an instruction register for storing a plurality of consecutive instructions read out from an address of the memory indicated by the program counter, a plurality of integer logic arithmetic units for executing integer-arithmetic operations, a floating-point arithmetic unit for executing floating-point-arithmetic operations, and a control unit for controlling the plurality of integer-logic arithmetic units and the floating-point arithmetic unit to effect either parallel processing of a plurality of consecutive instructions stored in the instruction register in the plurality of integer-logic arithmetic units and the floating-point arithmetic unit, or successive processing of instructions stored in the instruction register in response to a processing state alteration instruction. The apparatus also includes a branch arithmetic unit for executing branch arithmetic operations. The branch arithmetic unit is controlled by the control unit to effect parallel or consecutive processing of instructions in conjunction with the integer-logic and floating-point arithmetic units.

摘要翻译： 一种并行处理装置，包括用于指示要从存储器读出的指令的程序计数器，用于存储从由程序计数器指示的存储器的地址读出的多个连续指令的指令寄存器，多个整数逻辑运算 用于执行整数运算的单元，用于执行浮点算术运算的浮点运算单元，以及用于控制多个整数运算单元的控制单元和浮点运算单元，以进行并行处理 响应于处理状态改变指令，存储在多个整数逻辑运算单元和浮点运算单元中的指令寄存器中的多个连续指令或存储在指令寄存器中的指令的连续处理。 该装置还包括用于执行分支算术运算的分支运算单元。 分支运算单元由控制单元控制，以结合整数逻辑和浮点运算单元来执行指令的并行或连续处理。

公开(公告)号：US5404472A

公开(公告)日：1995-04-04

申请号：US149932

申请日：1993-11-10

申请人： Kenichi Kurosawa ,  Shigeya Tanaka ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh

发明人： Kenichi Kurosawa ,  Shigeya Tanaka ,  Yasuhiro Nakatsuka ,  Tadaaki Bandoh

IPC分类号： G06F9/318 ,  G06F9/38 ,  G06F12/08 ,  G06F15/177 ,  G06F9/445

CPC分类号： G06F9/30189 ,  G06F9/30181 ,  G06F9/3836 ,  G06F9/3842 ,  G06F9/3851 ,  G06F9/3861 ,  G06F9/3867 ,  G06F9/3885

摘要： When executing successive processing of conventional software, a parallel processing apparatus turns a processing state discrimination flag off, increases a program count by 1 at a time, reads out one instruction, and processes that instruction in an arithmetic unit. When executing parallel processing for new software, the parallel processing apparatus turns the processing state discrimination on, increases the program count by m at a time, reads out m instructions, and exercises parallel processing over m instructions in m arithmetic units. In order to select either of the above described two kinds of processing, a discrimination changeover instruction having function of changing over the processing state discrimination flag is added. Instructions are processed in arithmetic unit(s) in accordance with the processing state discrimination flag. In this way, successive processing and parallel processing are provided with compatibility and are selectively executed.

摘要翻译： 当执行常规软件的连续处理时，并行处理装置将处理状态判别标志关闭，一次将程序数增加1，读出一个指令，并在运算单元中处理该指令。 当执行新软件的并行处理时，并行处理装置将处理状态判别转为一次，一次增加程序数m，读出m个指令，并对m个运算单元中的m个指令进行并行处理。 为了选择上述两种处理之一，添加具有改变处理状态判别标志的功能的识别切换指令。 指令根据处理状态判别标志在算术单元中进行处理。 以这种方式，连续处理和并行处理具有兼容性并且被选择性地执行。

公开(公告)号：US5345560A

公开(公告)日：1994-09-06

申请号：US921742

申请日：1992-07-30

申请人： Shuuichi Miura ,  Kenichi Kurosawa ,  Tetsuaki Nakamikawa ,  Kenji Hirose

发明人： Shuuichi Miura ,  Kenichi Kurosawa ,  Tetsuaki Nakamikawa ,  Kenji Hirose

IPC分类号： G06F9/38 ,  G06F12/02 ,  G06F12/08

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F2212/6022 ,  G06F2212/6026

摘要： A prefetch buffer adapted to be installed between a cache memory and a main memory in a computer system having a CPU. The prefetch buffer includes a buffer storage having at least one entry for storing prefetched data and an address tag, which is to be used for searching the data, as a pair; a data searcher for searching, from the data stored in the buffer storage, for data having an address requested by the CPU; and an address estimator for determining an address of data to be prefetched next from the main memory, based on the address requested by the CPU and also on a history of the addresses of data prefetched in the past from the main memory; and an address generator for generating an address of data to be prefetched from the main memory. With this arrangement, it is possible to improve the hit ratio of the prefetch buffer regardless of the direction in which the access address varies.

摘要翻译： 一种适于安装在具有CPU的计算机系统中的高速缓冲存储器和主存储器之间的预取缓冲器。 预取缓冲器包括具有用于存储预取数据的至少一个条目和要用于搜索数据的地址标签作为一对的缓冲存储器; 数据搜索器，用于从存储在缓冲存储器中的数据中搜索具有由CPU请求的地址的数据; 以及地址估计器，用于基于所述CPU所请求的地址以及来自主存储器的过去预取的数据的地址的历史来确定要从主存储器预先预取的数据的地址; 以及地址发生器，用于从主存储器生成要预取的数据的地址。 利用这种布置，无论访问地址变化的方向如何，都可以提高预取缓冲器的命中率。

公开(公告)号：US4912152A

公开(公告)日：1990-03-27

申请号：US264388

申请日：1988-10-31

申请人： Kazumi Nejigaki ,  Kenichi Kurosawa ,  Isao Nishiwaki ,  Yukihiro Okubo

发明人： Kazumi Nejigaki ,  Kenichi Kurosawa ,  Isao Nishiwaki ,  Yukihiro Okubo

IPC分类号： C08G18/10 ,  C08G18/70

CPC分类号： C08G18/703 ,  C08G18/10 ,  C08G2190/00

摘要： A one-pack type thermosetting composition comprising (A) at least one polyisocyanate compound having dispersed therein (B) at least one compound selected from the group consisting of (1) a solid polyfunctional compound having at least one functional group selected from the group consisting of hydrazino, primary amido and sulfamoyl groups, (2) a solid compound having at least one amidino group and (3) a solid compound having a heterocyclic ring and a plurality of active hydrogen atoms, or a one-pack type thermosetting composition comprising (A') a mixture consisting of (a) at least one polyisocyanate compound and (b) at least one high boiling polar compound, having dispersed therein (B') a solid polyfunctional compound having at least one active hydrogen atom. Said one-pack type thermosetting composition is storable and suitable for use in adhesives, sealing materials, coatings and shaped articles of resin.

摘要翻译： 一种单组分型热固性组合物，其包含（A）至少一种其中分散有的多异氰酸酯化合物（B）至少一种选自以下的化合物：（1）具有至少一个选自以下的官能团的固体多官能化合物： 的肼基，伯酰胺基和氨磺酰基，（2）具有至少一个脒基的固体化合物和（3）具有杂环和多个活性氢原子的固体化合物，或单组分型热固性组合物，其包含（ A'）由（a）至少一种多异氰酸酯化合物和（b）至少一种分散在其中的高沸点极性化合物（B'）组成的混合物，其具有至少一个活性氢原子的固体多官能化合物。 所述单组分型热固性组合物可储存并适用于粘合剂，密封材料，涂料和成型树脂制品。