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131 条记录 (耗时 0.026 秒)

    EPI T-gate structure for CoSi2 extendibility
    32.
    发明授权
    EPI T-gate structure for CoSi2 extendibility 有权
    EPI T-gate结构，CoSi2可扩展性

    公开(公告)号：US07622339B2

    公开(公告)日：2009-11-24

    申请号：US11340049

    申请日：2006-01-26

    申请人： Mark D. Hall ,  Dharmesh Jawarani ,  Mehul D. Shroff ,  Edward O. Travis

    发明人： Mark D. Hall ,  Dharmesh Jawarani ,  Mehul D. Shroff ,  Edward O. Travis

    IPC分类号： H01L21/338

    CPC分类号： H01L21/28114 ,  H01L29/42376 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7833

    摘要： A semiconductor process and apparatus provide a T-shaped structure (96) formed from a polysilicon structure (10) and an epitaxially grown polysilicon layer (70) and having a narrower bottom critical dimension (e.g., at or below 40 nm) and a larger top critical dimension (e.g., at or above 40 nm) so that a silicide may be formed from a first material (such as CoSi2) in at least the upper region (90) of the T-shaped structure (96) without incurring the increased resistance caused by agglomeration and voiding that can occur with certain silicides at the smaller critical dimensions.

    摘要翻译： 半导体工艺和装置提供由多晶硅结构（10）和外延生长的多晶硅层（70）形成并且具有较窄的底部临界尺寸（例如，等于或低于40nm）形成的T形结构（96）和更大的 顶部临界尺寸（例如，在40nm以上），使得硅化物可以在至少T形结构（96）的上部区域（90）中由第一材料（例如CoSi 2）形成，而不会增加 在较小的临界尺寸下，某些硅化物可能会发生聚集和排空引起的电阻。

    Method for forming a split-gate device
    34.
    发明授权
    Method for forming a split-gate device 有权
    形成分闸装置的方法

    公开(公告)号：US09252152B2

    公开(公告)日：2016-02-02

    申请号：US14228678

    申请日：2014-03-28

    申请人： Mark D. Hall ,  Mehul D. Shroff

    发明人： Mark D. Hall ,  Mehul D. Shroff

    IPC分类号： H01L21/338 ,  H01L27/115 ,  H01L21/28 ,  H01L21/306 ,  H01L21/321 ,  H01L29/66 ,  H01L29/423 ,  H01L29/49 ,  H01L29/51 ,  H01L21/311 ,  H01L21/3105

    CPC分类号： H01L27/11568 ,  H01L21/31051 ,  H01L27/11534 ,  H01L27/11573 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/511 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881

    摘要： Forming a semiconductor device in an NVM region and in a logic region using a semiconductor substrate includes forming a dielectric layer and forming a first gate material layer over the dielectric layer. In the logic region, a high-k dielectric and a barrier layer are formed. A second gate material layer is formed over the barrier and the first material layer. Patterning results in gate-region fill material over the NVM region and a logic stack comprising a portion of the second gate material layer and a portion of the barrier layer in the logic region. An opening in the gate-region fill material leaves a select gate formed from a portion of the gate-region fill material adjacent to the opening. A control gate is formed in the opening over a charge storage layer. The portion of the second gate material layer is replaced with a metallic logic gate.

    摘要翻译： 在NVM区域和使用半导体衬底的逻辑区域中形成半导体器件包括形成电介质层并在电介质层上形成第一栅极材料层。 在逻辑区域中，形成高k电介质和阻挡层。 在阻挡层和第一材料层之上形成第二栅极材料层。 图案化导致NVM区域上的栅极区域填充材料和包括第二栅极材料层的一部分和逻辑区域中的势垒层的一部分的逻辑堆叠。 栅极填充材料中的开口离开由与开口相邻的栅极 - 区域填充材料的一部分形成的选择栅极。 在电荷存储层上的开口中形成控制栅极。 第二栅极材料层的部分被金属逻辑门替代。

    Method of making a logic transistor and non-volatile memory (NVM) cell
    35.
    发明授权
    Method of making a logic transistor and non-volatile memory (NVM) cell 有权
    制造逻辑晶体管和非易失性存储器（NVM）单元的方法

    公开(公告)号：US09231077B2

    公开(公告)日：2016-01-05

    申请号：US14195299

    申请日：2014-03-03

    申请人： Mehul D. Shroff ,  Mark D. Hall

    发明人： Mehul D. Shroff ,  Mark D. Hall

    IPC分类号： H01L21/338 ,  H01L29/66 ,  H01L29/40 ,  H01L21/3213

    CPC分类号： H01L29/66484 ,  H01L21/28273 ,  H01L21/32139 ,  H01L27/11534 ,  H01L29/401 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/66833

    摘要： A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal.

    摘要翻译： 形成半导体器件的方法包括在NVM区域和逻辑区域中的衬底上形成第一栅极层; 在NVM区域中的第一栅极层中形成开口; 在开口中形成电荷存储层; 在开口中的电荷存储层上形成控制栅极; 图案化第一栅极层以在逻辑区域中的衬底上形成第一图案化栅极层部分，并且在NVM区域中的衬底上形成第二图案化栅极层部分，其中第二图案化栅极层部分与控制栅极相邻; 在所述第一图案化栅极层部分周围以及所述第二图案化栅极层部分和所述控制栅极周围的所述基板上方形成介电层，并用包含金属的逻辑门代替所述第一图案化栅极层部分。

    Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique
    37.
    发明授权
    Integrating formation of a logic transistor and a non-volatile memory cell using a partial replacement gate technique 有权
    使用部分替代门技术集成逻辑晶体管和非易失性存储器单元的形成

    公开(公告)号：US08741719B1

    公开(公告)日：2014-06-03

    申请号：US13790014

    申请日：2013-03-08

    申请人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

    发明人： Mark D. Hall ,  Frank K. Baker, Jr. ,  Mehul D. Shroff

    IPC分类号： H01L21/8247

    CPC分类号： H01L27/11534 ,  H01L27/11524 ,  H01L29/66545

    摘要： A thermally-grown oxygen-containing gate dielectric and select gate are formed in an NVM region. A high-k gate dielectric, barrier layer, and dummy gate are formed in a logic region. The barrier layer may include a work-function-setting material. A first dielectric layer is formed in the NVM and logic regions which surrounds the select gate and dummy gate. The first dielectric layer is removed from the NVM region and protected in the logic region. A charge storage layer is formed over the select gate. The dummy gate is removed, resulting in an opening. A gate layer is formed over the charge storage layer in the NVM region and within the opening in the logic region, wherein the gate layer within the opening together with the barrier layer form a logic gate in the logic region, and the gate layer is patterned to form a control gate in the NVM region.

    摘要翻译： 在NVM区域中形成热生长含氧栅极电介质和选择栅极。 在逻辑区域中形成高k栅极电介质，势垒层和伪栅极。 阻挡层可以包括工作功能设定材料。 第一电介质层形成在NVM和围绕选择栅极和虚拟栅极的逻辑区域中。 从NVM区域去除第一介质层并在逻辑区域中保护。 在选择栅极上形成电荷存储层。 去除虚拟门，导致开口。 栅极层形成在NVM区域中的电荷存储层中并且在逻辑区域的开口内，其中开口内的栅极层与势垒层一起在逻辑区域中形成逻辑门，栅极层被图案化 以在NVM区域中形成控制门。

    Integration technique using thermal oxide select gate dielectric for select gate and replacement gate for logic
    39.
    发明授权
    Integration technique using thermal oxide select gate dielectric for select gate and replacement gate for logic 有权
    使用热氧化物选择栅极电介质的集成技术用于选择栅极和替代栅极用于逻辑

    公开(公告)号：US08524557B1

    公开(公告)日：2013-09-03

    申请号：US13789971

    申请日：2013-03-08

    申请人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, Jr.

    发明人： Mark D. Hall ,  Mehul D. Shroff ,  Frank K. Baker, Jr.

    IPC分类号： H01L21/8246

    CPC分类号： H01L29/66833 ,  H01L21/28282 ,  H01L27/1157 ,  H01L27/11573 ,  H01L29/42348

    摘要： A control gate overlying a charge storage layer is formed. A thermally-grown oxygen-containing layer is formed over the control gate. A polysilicon layer is formed over the oxygen-containing layer and planarized. A first masking layer is formed defining a select gate location laterally adjacent the control gate and a second masking layer is formed defining a logic gate location. Exposed portions of the polysilicon layer are removed such that a select gate remains at the select gate location and a polysilicon portion remains at the logic gate location. A dielectric layer is formed around the select and control gates and polysilicon portion. The polysilicon portion is removed to result in an opening in the dielectric. A high-k gate dielectric and logic gate are formed in the opening.

    摘要翻译： 形成覆盖电荷存储层的控制栅极。 在控制栅上形成热生长含氧层。 在含氧层上方形成多晶硅层并进行平坦化。 形成第一掩模层，其限定了横向邻近控制栅极的选择栅极位置，并且形成限定逻辑门位置的第二掩模层。 去除多晶硅层的暴露部分，使得选择栅极保留在选择栅极位置处，并且多晶硅部分保持在逻辑门位置。 在选择和控制栅极和多晶硅部分周围形成介电层。 去除多晶硅部分以导致电介质中的开口。 在开口中形成高k栅介质和逻辑门。

    NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION
    40.
    发明申请
    NON-VOLATILE MEMORY (NVM) AND LOGIC INTEGRATION 有权
    非易失性存储器（NVM）和逻辑集成

    公开(公告)号：US20130171785A1

    公开(公告)日：2013-07-04

    申请号：US13343331

    申请日：2012-01-04

    申请人： Mehul D. Shroff ,  Mark D. Hall

    发明人： Mehul D. Shroff ,  Mark D. Hall

    IPC分类号： H01L21/8239

    CPC分类号： B82Y10/00 ,  H01L21/28273 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11534 ,  H01L29/42328 ,  H01L29/42332 ,  H01L29/66545 ,  H01L29/66825 ,  H01L29/7881

    摘要： A method of forming an NVM cell and a logic transistor uses a semiconductor substrate. A metal select gate of the NVM cell is formed over a high-k dielectric as is metal logic gate of a logic transistor. The logic transistor is formed, including forming source/drains, while the metal select gate of the NVM cell is formed. The logic transistor is protected while the NVM cell is then formed including forming a charge storage region using metal nanocrystals and a metal control gate over a portion of the metal select gate and a portion of the charge storage region over the substrate. The charge storage region is etched to be aligned to the metal control gate.

    摘要翻译： 形成NVM单元和逻辑晶体管的方法使用半导体衬底。 NVM单元的金属选择栅极形成在高k电介质上，如逻辑晶体管的金属逻辑门。 在形成NVM单元的金属选择栅极的同时形成逻辑晶体管，包括形成源极/漏极。 逻辑晶体管被保护，同时形成NVM单元，包括在金属选择栅极的一部分和衬底上的电荷存储区域的一部分上使用金属纳米晶体和金属控制栅极形成电荷存储区域。 蚀刻电荷存储区域以与金属控制栅极对准。