中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

47 records (took 0.021 seconds)

    Semiconductor devices with redistribution structures configured for switchable routing
    32.
    发明授权
    Semiconductor devices with redistribution structures configured for switchable routing 有权

    公开(公告)号：US11791316B2

    公开(公告)日：2023-10-17

    申请号：US17521173

    申请日：2021-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Travis M. Jensen ,  David R. Hembree

    IPC: H01L25/065 ,  H01L25/00

    CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06586

    Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.

    STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND MOLDED UNDERFILL
    33.
    发明申请
    STACKED SEMICONDUCTOR DIE ASSEMBLIES WITH HIGH EFFICIENCY THERMAL PATHS AND MOLDED UNDERFILL 审中-公开

    公开(公告)号：US20200020547A1

    公开(公告)日：2020-01-16

    申请号：US16578647

    申请日：2019-09-23

    Applicant: Micron Technology, Inc.

    Inventor： David R. Hembree ,  William R. Stephenson

    IPC: H01L21/56 ,  H01L23/495 ,  H01L23/367

    Abstract: Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.

    SEMICONDUCTOR DEVICE ASSEMBLY WITH DIE SUPPORT STRUCTURES
    34.
    发明申请
    SEMICONDUCTOR DEVICE ASSEMBLY WITH DIE SUPPORT STRUCTURES 审中-公开

    公开(公告)号：US20180342475A1

    公开(公告)日：2018-11-29

    申请号：US15603175

    申请日：2017-05-23

    Applicant: Micron Technology, Inc.

    Inventor： Brandon P. Wirz ,  David R. Hembree

    IPC: H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L25/18

    Abstract: A semiconductor device assembly is provided. The assembly includes a first semiconductor die and a second semiconductor die disposed over the first semiconductor die. The assembly further includes a plurality of die support structures between the first and second semiconductor dies and a plurality of interconnects between the first and second semiconductor dies. Each of the plurality of die support structures includes a stand-off pillar and a stand-off pad having a first bond material with a first solder joint thickness between them. Each of the plurality of interconnects includes a conductive pillar and a conductive pad having a second bond material with a second solder joint thickness between them. The first solder joint thickness is less than the second solder joint thickness.

    Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill
    36.
    发明授权
    Stacked semiconductor die assemblies with high efficiency thermal paths and molded underfill 有权

    公开(公告)号：US10008395B2

    公开(公告)日：2018-06-26

    申请号：US15298156

    申请日：2016-10-19

    Applicant: Micron Technology, Inc.

    Inventor： David R. Hembree ,  William R. Stephenson

    IPC: H01L23/28 ,  H01L21/00 ,  H01L21/56 ,  H01L21/48 ,  H01L23/367 ,  H01L23/495

    Abstract: Semiconductor die assemblies having high efficiency thermal paths and molded underfill material. In one embodiment, a semiconductor die assembly comprises a first die and a plurality of second dies. The first die has a first functionality, a lateral region, and a stacking site. The second dies have a different functionality than the first die, and the second dies are in a die stack including a bottom second die mounted to the stacking site of the first die and a top second die defining a top surface of the die stack. A thermal transfer structure is attached to at least the lateral region of the first die and has a cavity in which the second dies are positioned. An underfill material is in the cavity between the second dies and the thermal transfer structure, and the underfill material covers the top surface of the die stack.

    Apparatuses and methods for internal heat spreading for packaged semiconductor die
    39.
    发明授权
    Apparatuses and methods for internal heat spreading for packaged semiconductor die 有权

    公开(公告)号：US11329026B2

    公开(公告)日：2022-05-10

    申请号：US15046078

    申请日：2016-02-17

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： David R. Hembree

    IPC: H01L23/367 ,  H01L25/065 ,  H01L23/42 ,  H01L23/053 ,  H01L23/31 ,  H01L25/18

    Abstract: Apparatuses and methods for internal heat spreading for packaged semiconductor die are disclosed herein. An example apparatus may include a plurality of die in a stack, a bottom die supporting the plurality of die, a barrier and a heat spreader. A portion of the bottom die may extend beyond the plurality of die and a top surface of the bottom die extending beyond the plurality of die may be exposed. The barrier may be disposed alongside the plurality of die and the bottom die, and the heat spreader may be disposed over the exposed top surface of the bottom die and alongside the plurality of die.

    SEMICONDUCTOR DEVICES WITH REDISTRIBUTION STRUCTURES CONFIGURED FOR SWITCHABLE ROUTING
    40.
    发明申请
    SEMICONDUCTOR DEVICES WITH REDISTRIBUTION STRUCTURES CONFIGURED FOR SWITCHABLE ROUTING 有权

    公开(公告)号：US20220059509A1

    公开(公告)日：2022-02-24

    申请号：US17521173

    申请日：2021-11-08

    Applicant: Micron Technology, Inc.

    Inventor： Travis M. Jensen ,  David R. Hembree

    IPC: H01L25/065 ,  H01L25/00

    Abstract: Semiconductor devices having redistribution structures, and associated systems and methods, are disclosed herein. In one embodiment, a semiconductor package includes a first semiconductor die including a first redistribution structure and a second semiconductor die including a second redistribution structure. The first and second semiconductor dies can be mounted on a package substrate such that the first and second redistribution structures are aligned with each other. In some embodiments, an interconnect structure can be positioned between the first and second semiconductor dies to electrically couple the first and second redistribution structures to each other. The first and second redistribution structures can be configured such that signal routing between the first and second semiconductor dies can be altered based on the location of the interconnect structure.

Patent Agency Ranking