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    VARIABLE FILTER CAPACITANCE
    33.
    发明申请
    VARIABLE FILTER CAPACITANCE 审中-公开

    公开(公告)号：US20190035441A1

    公开(公告)日：2019-01-31

    申请号：US16020834

    申请日：2018-06-27

    申请人： Micron Technology, Inc.

    发明人： Ferdinando Bedeschi ,  Umberto Di Vincenzo

    IPC分类号： G11C7/14 ,  G11C11/24 ,  G11C11/22 ,  G11C11/408

    CPC分类号： G11C7/14 ,  G11C5/063 ,  G11C5/147 ,  G11C8/08 ,  G11C8/14 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2297 ,  G11C11/24 ,  G11C11/408

    摘要： Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array.

    Resistive memory cell structures and methods
    34.
    发明授权
    Resistive memory cell structures and methods 有权

    公开(公告)号：US10147763B2

    公开(公告)日：2018-12-04

    申请号：US15836978

    申请日：2017-12-11

    申请人： Micron Technology, Inc.

    发明人： Fabio Pellizzer ,  Ferdinando Bedeschi

    IPC分类号： H01L27/24 ,  H01L45/00

    摘要： Resistive memory cell structures and methods are described herein. One or more memory cell structures comprise a first resistive memory cell comprising a first resistance variable material and a second resistive memory cell comprising a second resistance variable material that is different than the first resistance variable material.

    COMPENSATING FOR VARIATIONS IN SELECTOR THRESHOLD VOLTAGES
    35.
    发明申请
    COMPENSATING FOR VARIATIONS IN SELECTOR THRESHOLD VOLTAGES 有权

    公开(公告)号：US20180102157A1

    公开(公告)日：2018-04-12

    申请号：US15291711

    申请日：2016-10-12

    申请人： Micron Technology, Inc.

    发明人： Ferdinando Bedeschi ,  Umberto Di Vincenzo

    IPC分类号： G11C11/22

    CPC分类号： G11C11/2259 ,  G11C11/221 ,  G11C11/2273 ,  G11C11/2275 ,  G11C11/2277 ,  G11C11/2293

    摘要： Methods, systems, and devices are described for operating a memory array. A first voltage may be applied to a memory cell to activate a selection component of the memory cell prior to applying a second voltage to the memory cell. The second voltage may be applied to facilitate a sensing operation once the selection component is activated. The first voltage may be applied during a first portion of an access operation and may be used in determining a threshold voltage of the selection component. The subsequently applied second voltage may be applied during a second portion of the access operation and may have a magnitude associated with a preferred voltage for accessing a ferroelectric capacitor of the memory cell. In some cases, the second voltage has a greater rate of increase over time (e.g., a greater “ramp”) than the first voltage.

    FULL BIAS SENSING IN A MEMORY ARRAY
    36.
    发明申请
    FULL BIAS SENSING IN A MEMORY ARRAY 审中-公开

    公开(公告)号：US20180061470A1

    公开(公告)日：2018-03-01

    申请号：US15246249

    申请日：2016-08-24

    申请人： Micron Technology, Inc.

    发明人： Umberto Di Vincenzo ,  Ferdinando Bedeschi

    IPC分类号： G11C11/22

    CPC分类号： G11C11/2273 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2275

    摘要： Methods, systems, and apparatuses for full bias sensing in a memory array are described. Various embodiments of an access operation of a cell in a array may be timed to allow residual charge of a middle electrode between the cell and a selection component to discharge. Access operations may also be timed to allow residual charge of middle electrodes associated with other cells to be discharged. In conjunction with an access operation for a target cell, a residual charge of a middle electrode of another cell may be discharged, and the target cell may then be accessed. A capacitor in electronic communication with a cell may be charged and a logic state of the cell determined based on the charge of the capacitor. The timing for charging the capacitor may be related to the time for discharging a middle electrode of the cell or another cell.

    SENSE CIRCUITS, MEMORY DEVICES, AND RELATED METHODS FOR RESISTANCE VARIABLE MEMORY
    38.
    发明申请
    SENSE CIRCUITS, MEMORY DEVICES, AND RELATED METHODS FOR RESISTANCE VARIABLE MEMORY 有权
    感知电路，存储器件和相关的电阻可变存储器的方法

    公开(公告)号：US20170040045A1

    公开(公告)日：2017-02-09

    申请号：US15258204

    申请日：2016-09-07

    申请人： Micron Technology, Inc.

    发明人： Michele Piccardi ,  Ferdinando Bedeschi

    IPC分类号： G11C11/16

    CPC分类号： G11C11/1673 ,  G11C7/06 ,  G11C11/161 ,  G11C11/1693 ,  G11C11/5607 ,  G11C13/0002 ,  G11C13/0035 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0045 ,  G11C2013/0047 ,  G11C2013/0057

    摘要： Sense circuits, memory devices, and related methods are disclosed. A sense circuit includes sample and hold circuitry configured to sample and hold a second response voltage potential, a first response voltage potential, and a third response voltage potential responsive to an evaluation signal applied to a resistance variable memory cell. The sense circuit includes an amplifier operably coupled to the sample and hold circuitry. The amplifier is configured to amplify a difference between a sum of the first response voltage potential and the third response voltage potential, and twice the second response voltage potential. A memory device includes an evaluation signal generating circuit configured to provide the evaluation signal, an array of resistance variable memory cells, and the sense circuit. A method includes applying the evaluation signal to the resistance variable memory cell, sampling and holding the response voltage potentials, and discharging the sample and hold circuitry to the amplifier.

    摘要翻译： 感测电路，存储器件和相关方法被公开。 感测电路包括采样和保持电路，其被配置为响应于施加到电阻变量存储单元的评估信号来采样和保持第二响应电压电位，第一响应电压电位和第三响应电压电位。 感测电路包括可操作地耦合到采样和保持电路的放大器。 放大器被配置为放大第一响应电压电位和第三响应电压电位之和与第二响应电压电位的两倍之间的差。 存储器件包括：评估信号发生电路，被配置为提供评估信号，电阻可变存储单元阵列和感测电路。 一种方法包括将评估信号施加到电阻可变存储单元，采样并保持响应电压电位，并将取样和保持电路放电到放大器。

    APPARTUSES AND METHODS FOR SENSING USING AN INTEGRATION COMPONENT
    40.
    发明申请
    APPARTUSES AND METHODS FOR SENSING USING AN INTEGRATION COMPONENT 有权
    使用集成组件进行感应的方法和方法

    公开(公告)号：US20160049194A1

    公开(公告)日：2016-02-18

    申请号：US14458813

    申请日：2014-08-13

    申请人： Micron Technology, Inc.

    发明人： Ferdinando Bedeschi

    IPC分类号： G11C13/00

    CPC分类号： G11C13/004 ,  G11C11/00 ,  G11C11/1677 ,  G11C13/0064 ,  G11C2013/0066

    摘要： The present disclosure includes apparatuses and methods for sensing a resistance variable memory cell. A number of embodiments include circuitry to provide a programming signal to a memory cell in the array, the programming signal associated with programming the memory cell to a particular data state; and determine, via an integration component, if a data state of the memory cell changes to a different data state responsive to the programming signal being provided.

    摘要翻译： 本公开包括用于感测电阻变量存储单元的装置和方法。 许多实施例包括向阵列中的存储器单元提供编程信号的电路，与将存储器单元编程为特定数据状态相关联的编程信号; 并且通过积分分量确定响应于所提供的编程信号，存储器单元的数据状态是否变为不同的数据状态。