公开(公告)号：US20190286328A1

公开(公告)日：2019-09-19

申请号：US16428011

申请日：2019-05-31

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US10359963B2

公开(公告)日：2019-07-23

申请号：US15532886

申请日：2017-01-23

Applicant: Micron Technology, Inc.

Inventor： Sivagnanam Parthasarathy ,  Terry M. Grunzke ,  Lucia Botticchio ,  Walter Di Francesco ,  Vamshi K. Indavarapu ,  Gianfranco Valeri ,  Renato C. Padilla ,  Ali Mohammadzadeh ,  Jung Sheng Hoei ,  Luca De Santis

IPC: G06F3/06 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F3/064 ,  G06F3/0611 ,  G06F3/0659 ,  G06F3/0679 ,  G06F3/0688 ,  G06F12/0246 ,  G06F12/1009 ,  G06F2212/1021 ,  G06F2212/2022 ,  G06F2212/7201

Abstract: The present disclosure relates to partially written block treatment. An example method comprises maintaining, internal to a memory device, a status of a last written page corresponding to a partially written block. Responsive to receiving, from a controller, a read request to a page of the partially written block, the example method can include determining, from page map information maintained internal to the memory device and from the status of the last written page, which of a number of different read trim sets to use to read the page of the partially written block corresponding to the read request.

公开(公告)号：US10141055B2

公开(公告)日：2018-11-27

申请号：US15841490

申请日：2017-12-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

IPC: G11C15/00 ,  G11C15/04 ,  G11C16/10 ,  G11C16/04 ,  G11C29/52

Abstract: Methods include receiving a pattern to be searched in a memory having a plurality of sets of memory elements with each set coupled to a separate data line and corresponding to a same set of bit positions of the pattern. Methods further include receiving a pattern of data to be programmed into a memory, programming a first data state into one memory cell of each cell pair of a plurality of cell pairs of a memory array, and programing a second data state into another memory cell of each cell pair of the plurality of cell pairs for each bit position of the pattern. Memory configured to facilitate such methods include a plurality of cell pairs, each cell pair of the plurality of cell pairs programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in the memory.

公开(公告)号：US20180294035A1

公开(公告)日：2018-10-11

申请号：US16009541

申请日：2018-06-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommasso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis

IPC: G11C16/26 ,  G11C16/08 ,  G11C7/10 ,  G06N3/04 ,  G11C16/04 ,  G06N3/063

CPC classification number: G11C16/26 ,  G06N3/04 ,  G06N3/0454 ,  G06N3/063 ,  G11C7/1006 ,  G11C7/106 ,  G11C16/0483 ,  G11C16/08

Abstract: Methods of operating memory include generating a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line. Methods of operating memory further include generating data values indicative of levels of a property sensed from data lines while applying potentials to control gates of memory cells of strings of series-connected memory cells connected to those data lines, performing a logical operation on a set of data values comprising those data values, and determining a potential to be applied to control gates of different memory cells of those strings of series-connected memory cells in response to an output of the logical operation on the set of data values.

公开(公告)号：US20180294032A1

公开(公告)日：2018-10-11

申请号：US16003357

申请日：2018-06-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34 ,  G11C16/26

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

Abstract: Memories including a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells, as well as methods of operating similar memories.

公开(公告)号：US10089359B2

公开(公告)日：2018-10-02

申请号：US15253965

申请日：2016-09-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Giulio G. Marotta ,  Marco-Domenico Tiburzi ,  Tommaso Vali ,  Frankie F. Roohparvar ,  Agostino Macerola

IPC: G06F11/263 ,  G06F17/30 ,  G06F3/06 ,  G11C16/06 ,  G11C7/10 ,  G11C15/04 ,  G11C16/04 ,  G06F7/20 ,  G06F12/0802 ,  G11C29/50

Abstract: Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.

公开(公告)号：US10055293B2

公开(公告)日：2018-08-21

申请号：US15583678

申请日：2017-05-01

Applicant: Micron Technology, Inc.

Inventor： Violante Moschiano ,  Walter Di Francesco ,  Luca De Santis ,  Giovanni Santin

IPC: G11C29/00 ,  G06F11/10 ,  H03M13/37 ,  G11C29/02 ,  G11C29/52 ,  H03M13/11 ,  G11C29/04 ,  H03M13/45

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/1076 ,  G11C29/02 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0411 ,  H03M13/1102 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/2906 ,  H03M13/3715 ,  H03M13/45

Abstract: A memory device includes a memory array that includes a buffer data. The memory device also includes a memory controller. The memory controller includes an error correction code (ECC) component. The memory controller further receives a status command and an indication related to the quality of the data to analyze with the ECC component. Based on a status value, the memory controller utilizes one of a plurality of error correction techniques via the ECC component to correct an error (e.g., soft state, calibration, etc.).

公开(公告)号：US20170365342A1

公开(公告)日：2017-12-21

申请号：US15690359

申请日：2017-08-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

Abstract: Methods for operating a memory, and memory configured to perform similar methods, include programming a first series string of memory cells of a first group of memory cells such that pairs of complementary memory cells have complementary states to provide a first minterm, the first minterm comprising a plurality of first variables wherein each variable is enabled responsive to a state of its respective memory cell, and programming a second series string of memory cells of a second group of memory cells such that pairs of complementary memory cells have complementary states to provide a second minterm, the second minterm comprising the first minterm that is enabled responsive to the state of its respective memory cell, the second minterm further comprising a plurality of second variables that are each enabled responsive to the state of their respective memory cell.

公开(公告)号：US09772779B2

公开(公告)日：2017-09-26

申请号：US15098574

申请日：2016-04-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Luigi Pilolli

IPC: G11C5/14 ,  G06F3/06 ,  G11C11/4074 ,  G11C16/10 ,  G11C7/16 ,  G11C11/4096 ,  G11C7/10 ,  G06F13/16 ,  G11C16/06 ,  G06F12/0875 ,  G06F12/0893

CPC classification number: G06F3/061 ,  G06F3/0659 ,  G06F3/0688 ,  G06F12/0875 ,  G06F12/0893 ,  G06F13/1668 ,  G06F2212/2022 ,  G06F2212/452 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/16 ,  G11C11/4074 ,  G11C11/4096 ,  G11C16/06 ,  G11C16/10 ,  G11C2207/2245 ,  Y02D10/13 ,  Y02D10/14

Abstract: Methods for operating a distributed controller system in a memory device include receiving a read command, a master controller generating an indication to a data cache controller in response to the read command, and the data cache controller accepting data from a memory array of the memory device in response to the indication.

公开(公告)号：US09728267B2

公开(公告)日：2017-08-08

申请号：US14798845

申请日：2015-07-14

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C15/04 ,  G11C16/28 ,  G11C15/00 ,  G11C16/04

CPC classification number: G11C16/28 ,  G11C15/00 ,  G11C15/046 ,  G11C16/0483

Abstract: A memory device has first and second strings of memory cells coupled to a data line. The first string is for storing a first bit having a first bit significance, and the second string is for storing a second bit having a second bit significance different than the first bit significance. A first resistor is coupled in series with the first string. A second resistor is coupled in series with the second string. The memory device is configured to set the first resistor to a first resistance based on the first bit significance and the second resistor to a second resistance based on the second bit significance so that the second resistance is different than the first resistance. The memory device is configured to compare a first bit of input data to the first bit and to compare a second bit of the input data to the second bit.