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公开(公告)号：US10854303B2
公开(公告)日：2020-12-01
申请号：US16908832
申请日：2020-06-23
发明人： Tommaso Vali , Ramin Ghodsi
摘要： Methods of operating a memory, as well as memory configured to perform such methods, might include determining a plurality of read voltages for a read operation during a precharge phase of the read operation, determining a pass voltage for the read operation during the precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.
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公开(公告)号：US10714196B2
公开(公告)日：2020-07-14
申请号：US16152897
申请日：2018-10-05
发明人： Tommaso Vali , Ramin Ghodsi
摘要： Methods of operating a memory might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, determining a particular voltage level at which the state of each data line of a first subset of the plurality of data lines has changed, decreasing a voltage level applied to a particular access line of the plurality of access lines, and sensing a state of each data line of a second subset of the plurality of data lines while applying the particular voltage level to the particular access line. Methods of operating a memory might further include determining a pass voltage and plurality of read voltages for a read operation during a precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.
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公开(公告)号：US20200211660A1
公开(公告)日：2020-07-02
申请号：US16267488
申请日：2019-02-05
发明人： Violante Moschiano , Tecla Ghilardi , Tommaso Vali , Emilio Camerlenghi , William C. Filipiak , Andrea D'Alessandro
IPC分类号： G11C16/34 , G11C16/26 , G11C5/06 , G11C11/413 , G11C8/08
摘要： Methods of operating a memory, and memory configured to perform similar methods, might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, ceasing increasing the voltage level applied to each access line of the plurality of access lines in response to the state of each data line of the plurality of data lines having a particular condition, changing a voltage level applied to a particular access line of the plurality of access lines to a particular voltage level, and sensing a state of each data line of a subset of the plurality of data lines while applying the particular voltage level to the particular access line.
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公开(公告)号：US20200211648A1
公开(公告)日：2020-07-02
申请号：US16235066
申请日：2018-12-28
发明人： Umberto Minucci , Tommaso Vali , Fernanda Irrera , Luca De Santis
摘要： A method can include applying a first voltage to a first memory cell to activate the first memory cell, applying a second voltage to a second memory cell coupled in series with the first memory cell to activate the second memory cell so that current flows through the first and second memory cells, and generating an output responsive to the current. The first voltage and a threshold voltage of the second memory cell can be such that the current is proportional to a product of the first voltage and the threshold voltage of the second memory cell.
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公开(公告)号：US20200111534A1
公开(公告)日：2020-04-09
申请号：US16152897
申请日：2018-10-05
发明人： Tommaso Vali , Ramin Ghodsi
摘要： Methods of operating a memory might include sensing a state of each data line of a plurality of data lines while increasing a voltage level applied to each access line of a plurality of access lines commonly connected to a plurality of strings of series-connected memory cells, determining a particular voltage level at which the state of each data line of a first subset of the plurality of data lines has changed, decreasing a voltage level applied to a particular access line of the plurality of access lines, and sensing a state of each data line of a second subset of the plurality of data lines while applying the particular voltage level to the particular access line. Methods of operating a memory might further include determining a pass voltage and plurality of read voltages for a read operation during a precharge phase of the read operation, applying the pass voltage to each unselected access line of a plurality of access lines, and, for each read voltage of the plurality of read voltages, applying that read voltage to a selected access line of the plurality of access lines and sensing a data state of a memory cell connected to the selected access line.
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公开(公告)号：US10409673B2
公开(公告)日：2019-09-10
申请号：US15414699
申请日：2017-01-25
IPC分类号： G11C29/00 , G06F11/10 , G11C11/56 , G11C16/04 , G11C16/10 , G06F3/06 , G06F12/02 , G06F12/06 , G11C29/52
摘要： A memory device has a plurality of individually erasable blocks of memory cells and a controller configured to configure a first block of the plurality of blocks of memory cells in a first configuration comprising one or more groups of overhead data memory cells, to configure a second block of the plurality of blocks of memory cells in a second configuration comprising a group of user data memory cells and a group of overhead data memory cells, and to configure a third block of the plurality of blocks of memory cells in a third configuration comprising only a group of user data memory cells. The group of overhead data memory cells of the second block of memory cells has a different storage capacity than at least one group of overhead data memory cells of the one or more groups of overhead data memory cells of the first block.
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公开(公告)号：US10395740B2
公开(公告)日：2019-08-27
申请号：US16003357
申请日：2018-06-08
摘要： Memories including a data line, a plurality of strings of series-connected memory cells selectively connected to the data line, a plurality of first access lines each coupled to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells, and a plurality of second access lines each coupled to a control gate of a respective memory cell of a respective string of series-connected memory cells of the plurality of strings of series-connected memory cells, as well as methods of operating similar memories.
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公开(公告)号：US20190050162A1
公开(公告)日：2019-02-14
申请号：US16166231
申请日：2018-10-22
CPC分类号： G06F3/0634 , G06F3/0626 , G06F3/0632 , G06F3/0679 , G06F3/0688 , G06F11/1064 , G06F11/2263 , G11C11/005 , G11C15/046 , G11C16/0483
摘要： Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.
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公开(公告)号：US20180365293A1
公开(公告)日：2018-12-20
申请号：US16113055
申请日：2018-08-27
发明人： Luca De Santis , Giulio G. Marotta , Marco-Domenico Tiburzi , Tommaso Vali , Frankie F. Roohparvar , Agostino Macerola
IPC分类号： G06F17/30 , G11C16/04 , G11C29/50 , G06F12/0802 , G06F3/06 , G06F7/20 , G11C7/10 , G11C16/06 , G11C15/04
CPC分类号： G06F16/24558 , G06F3/0628 , G06F7/20 , G06F12/0802 , G06F2212/1021 , G06F2212/608 , G11C7/1006 , G11C15/046 , G11C16/0483 , G11C16/06 , G11C29/50004 , G11C29/50016
摘要： Memory devices for facilitating pattern matching and having an array of memory cells, a plurality of key registers to store a representation of a key word, and a plurality of multiplexers, each multiplexer of the plurality of multiplexers to select a representation of a bit from a key register of the plurality of key registers to compare to data stored in the array of memory cells.
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公开(公告)号：US10134481B2
公开(公告)日：2018-11-20
申请号：US15449426
申请日：2017-03-03
发明人： Tommaso Vali , Andrea D'Alessandro , Violante Moschiano , Mattia Cichocki , Michele Incarnati , Federica Paolini
摘要： Methods of operating a memory include storing a first target data state of multiple possible data states of a first memory cell to be programmed in a target data latch coupled to a data node, storing at least one bit of a second target data state of the multiple possible data states of a second memory cell to be programmed in an aggressor data latch coupled to the data node, and programming the first memory cell and performing a program verify operation for the first target data state to determine if the first memory cell is verified for the first target data state. The program verify operation including: an intermediate verify corresponding to an amount of aggression to apply a voltage to the data node when performing the intermediate verify, based on the at least one bit of the second target state stored in the aggressor data latch; and a program verify corresponding to a condition of no aggression to apply to the voltage to the data node when performing the program verify, based on the at least one bit of the second target state stored in the aggressor data latch. The methods including inhibiting the first memory cell from further programming if the first memory cell is verified during the intermediate verify and the at least one bit in the aggressor data latch corresponds to the particular amount of aggression, or the first memory cell is verified during the program verify and the at least one bit in the aggressor data latch corresponds to the condition of no aggression. The second memory cell is a neighbor of the first memory cell.
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