公开(公告)号：US20070284678A1

公开(公告)日：2007-12-13

申请号：US11838376

申请日：2007-08-14

Applicant: Chen-Tung Lin ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Mei-Yun Wang ,  Chiang-Ming Chuang ,  Shau-Lin Shue

Inventor： Chen-Tung Lin ,  Chih-Wei Chang ,  Chii-Ming Wu ,  Mei-Yun Wang ,  Chiang-Ming Chuang ,  Shau-Lin Shue

IPC: H01L21/3205 ,  H01L29/45

CPC classification number: H01L29/66545 ,  H01L21/28061 ,  H01L21/28097 ,  H01L21/28525 ,  H01L21/76877 ,  H01L21/76889 ,  H01L23/485 ,  H01L2924/0002 ,  Y10S438/926 ,  H01L2924/00

Abstract: A method of manufacturing a microelectronic device including forming a dielectric layer surrounding a dummy feature located over a substrate, removing the dummy feature to form an opening in the dielectric layer, and forming a metal-silicide layer conforming to the opening by a metal deposition process employing a target which includes metal and silicon. The metal-silicide layer may then be annealed.

Abstract translation: 一种制造微电子器件的方法，包括形成围绕位于衬底上的虚拟特征的介电层，去除虚拟特征以在电介质层中形成开口，以及通过金属沉积工艺形成符合开口的金属硅化物层 使用包括金属和硅的靶。 然后可以将金属硅化物层退火。

公开(公告)号：US07282450B2

公开(公告)日：2007-10-16

申请号：US10733722

申请日：2003-12-11

Applicant: Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

Inventor： Shau-Lin Shue ,  Mei-Yun Wang ,  Chen-Hua Yu

IPC: H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/2855 ,  H01L21/76862 ,  H01L21/76865 ,  H01L21/76873 ,  H01L21/76874 ,  H01L2221/1089

Abstract: A general process is described for filling a hole or trench at the surface of an integrated circuit without trapping voids within the filler material. A particular application is the filling of a trench with copper in order to form damascene wiring. First, a seed layer is deposited in the hole or trench by means of PVD. This is then followed by a sputter etching step which removes any overhang of this seed layer at the mouth of the trench or hole. A number of process variations are described including double etch/deposit steps, varying pressure and voltage in the same chamber to allow sputter etching and deposition to take place without breaking vacuum, and reduction of contact resistance between wiring levels by reducing via depth.

Abstract translation: 描述了在集成电路的表面处填充孔或沟槽而不在填充材料内捕获空隙的一般方法。 具体应用是用铜填充沟槽以形成镶嵌线。 首先，通过PVD将种子层沉积在孔或沟槽中。 然后进行溅射蚀刻步骤，其移除沟槽或孔口处的该种子层的任何突出端。 描述了许多工艺变化，包括双重蚀刻/沉积步骤，在相同的室中改变压力和电压，以允许在不破坏真空的情况下进行溅射蚀刻和沉积，并且通过减小通孔深度来降低布线水平之间的接触电阻。

公开(公告)号：US20070221993A1

公开(公告)日：2007-09-27

申请号：US11389309

申请日：2006-03-27

Applicant: Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cp Lo ,  Chih-W Chang

Inventor： Shau-Lin Shue ,  Chen-Hua Yu ,  Cheng-Tung Lin ,  Chii-Ming Wu ,  Shih-Wei Chou ,  Gin Wang ,  Cp Lo ,  Chih-W Chang

IPC: H01L27/12 ,  H01L27/01 ,  H01L31/0392

CPC classification number: H01L29/665 ,  H01L21/76243 ,  H01L29/785

Abstract: A semiconductor device and method of manufacturing are provided that include forming an alloy layer having the formula MbX over a silicon-containing substrate, where Mb is a metal and X is an alloying additive, the alloy layer being annealed to form a metal alloy silicide layer on the gate region and in active regions of the semiconductor device.

Abstract translation: 提供一种半导体器件和制造方法，包括在含硅衬底上形成具有式MbX的合金层，其中Mb是金属，X是合金添加剂，合金层被退火以形成金属合金硅化物层 在栅极区域和半导体器件的有源区中。

公开(公告)号：US20070181434A1

公开(公告)日：2007-08-09

申请号：US11783245

申请日：2007-04-06

Applicant: Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

Inventor： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC: C25D5/34 ,  H01L21/44 ,  C25D3/38

CPC classification number: H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

Abstract translation: 电化学沉积（ECD）的方法在衬底上提供阻挡层和种子层。 在将金属层电化学沉积在具有物理或化学表面处理工艺的电化学镀覆电池中之前，对基板的表面进行预处理。 电化学镀覆电池被盖覆盖以防止电解质溶液的蒸发。 电化学电镀单元包括具有提升密封件的衬底保持器组件，例如在提升密封件和衬底之间的接触角θ小于90°。 衬底保持器组件包括在衬底的后侧的衬底卡盘。

公开(公告)号：US07071095B2

公开(公告)日：2006-07-04

申请号：US10850763

申请日：2004-05-20

Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L21/4763

CPC classification number: H01L21/76865 ,  H01L21/02046 ,  H01L21/2855 ,  H01L21/32131 ,  H01L21/76843 ,  H01L21/76862

Abstract: A novel process for re-distributing a barrier layer deposited on a single damascene, dual damascene or other contact opening structure. The process includes providing a substrate having a contact opening structure and a metal barrier layer deposited in the contact opening structure, re-sputtering the barrier layer by bombarding the barrier layer with argon ions and metal ions, and re-sputtering the barrier layer by bombarding the barrier layer with argon ions.

Abstract translation: 一种用于重新分布沉积在单个镶嵌，双镶嵌或其他接触开口结构上的阻挡层的新方法。 该方法包括提供具有接触开口结构的衬底和沉积在接触开口结构中的金属阻挡层，通过用氩离子和金属离子轰击阻挡层来重新溅射阻挡层，并通过轰击来重新溅射阻挡层 阻挡层具有氩离子。

公开(公告)号：US20060118962A1

公开(公告)日：2006-06-08

申请号：US11004767

申请日：2004-12-03

Applicant: Jui Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

Inventor： Jui Huang ,  Minghsing Tsai ,  Shau-Lin Shue ,  Hung-Wen Su ,  Ting-Chu Ko

IPC: H01L23/48 ,  H01L23/52

CPC classification number: H01L21/76838 ,  H01L21/76805 ,  H01L21/76807 ,  H01L21/76834 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an integrated circuit interconnect structure is presented. A first conductive line is formed over a semiconductor substrate. A conductive cap layer is formed on the first conductive line to improve device reliability. An etch stop layer (ESL) is formed on the conductive cap layer. An inter-level dielectric (IMD) is formed on the ESL. A via opening and a trench are formed in the ESL, IMD, and conductive cap layer. A recess is formed in the first conductive line. The recess can be formed by over etching when the first dielectric is etched, or by a separate process such as argon sputtering. A second conductive line is formed filling the trench, opening and recess.

Abstract translation: 提出了一种形成集成电路互连结构的方法。 在半导体衬底上形成第一导电线。 导电盖层形成在第一导电线上以提高器件的可靠性。 在导电盖层上形成蚀刻停止层（ESL）。 在ESL上形成层间电介质（IMD）。 通孔和沟槽形成在ESL，IMD和导电盖层中。 在第一导线中形成凹部。 当蚀刻第一电介质时，或者通过诸如氩气溅射的分离工艺，可以通过过蚀刻形成凹部。 形成第二导电线，填充沟槽，开口和凹陷。

公开(公告)号：US20060099802A1

公开(公告)日：2006-05-11

申请号：US10985149

申请日：2004-11-10

Applicant: Jing-Cheng Lin ,  Shau-Lin Shue

Inventor： Jing-Cheng Lin ,  Shau-Lin Shue

IPC: H01L21/4763

CPC classification number: H01L21/76814 ,  H01L21/76826 ,  H01L21/76831

Abstract: A semiconductor structure having a via formed in a dielectric layer is provided. The exposed pores of the dielectric material along the sidewalls of the via are partially or completely sealed. Thereafter, one or more barrier layers may be formed and the via may be filled with a conductive material. The barrier layers formed over the sealing layer exhibits a more continuous barrier layer. The pores may be partially or completely sealed by performing, for example, a plasma process in an argon environment.

Abstract translation: 提供了具有形成在电介质层中的通孔的半导体结构。 沿着通孔的侧壁的电介质材料的暴露的孔部分或完全密封。 此后，可以形成一个或多个阻挡层，并且可以用导电材料填充通孔。 形成在密封层之上的阻挡层表现出更连续的阻挡层。 通过在氩气环境中进行例如等离子体处理，可以将孔部分或完全密封。

公开(公告)号：US20050266679A1

公开(公告)日：2005-12-01

申请号：US10995752

申请日：2004-11-23

Applicant: Jing-Cheng Lin ,  Shau-Lin Shue

Inventor： Jing-Cheng Lin ,  Shau-Lin Shue

IPC: H01L21/768 ,  H01L21/4763 ,  H01L23/52

CPC classification number: H01L21/76843 ,  H01L21/76805 ,  H01L21/76844 ,  H01L21/76865

Abstract: A via having a unique barrier layer structure is provided. In an embodiment, a via is formed by forming a barrier layer in a via. The barrier layer along the bottom of the via is partially or completely removed, and the via is filled with a conductive material. In another embodiment, a first barrier layer is formed along the bottom and sidewalls of the via. Thereafter, the first barrier layer along the bottom of the via is partially or completely removed, and a second barrier layer is formed.

Abstract translation: 提供具有独特的阻挡层结构的通孔。 在一个实施例中，通孔在通孔中形成阻挡层而形成通孔。 沿着通孔底部的阻挡层被部分地或完全去除，并且通孔用导电材料填充。 在另一个实施例中，沿着通孔的底部和侧壁形成第一阻挡层。 此后，沿通孔底部的第一阻挡层被部分地或完全地去除，形成第二阻挡层。

公开(公告)号：US20050239288A1

公开(公告)日：2005-10-27

申请号：US10910182

申请日：2004-08-02

Applicant: Chao-Hsien Peng ,  Jing-Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Chao-Hsien Peng ,  Jing-Cheng Lin ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76831 ,  H01L21/02046 ,  H01L21/32136 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838

Abstract: A method for forming a barrier layer upon a copper containing conductor layer employs a hydrogen containing plasma treatment of the copper containing conductor layer followed by an argon plasma treatment of the copper containing conductor layer. The barrier layer may be formed employing a chemical vapor deposition method, such as an atomic layer deposition method. When the deposition method employs a metal and carbon containing source material, the two-step plasma pretreatment provides the barrier layer with enhanced electrical properties.

Abstract translation: 在含铜导体层上形成阻挡层的方法采用含铜导体层的含氢等离子体处理，然后进行含铜导体层的氩等离子体处理。 可以使用诸如原子层沉积方法的化学气相沉积方法形成阻挡层。 当沉积方法采用含金属和碳的源材料时，两步等离子体预处理为阻挡层提供了增强的电性能。

公开(公告)号：US06949472B1

公开(公告)日：2005-09-27

申请号：US10838720

申请日：2004-05-03

Applicant: Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

Inventor： Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue

IPC: H01L21/306 ,  H01L21/31 ,  H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/02046 ,  H01L21/76862 ,  H01L21/76865

Abstract: A novel method for depositing a barrier layer on a single damascene, dual damascene or other contact opening structure. The method eliminates the need for pre-cleaning argon ion bombardment of the structure, thereby reducing or eliminating damage to the surface of the underlying conductive layer and sputtering of copper particles to the via or other contact opening sidewall. The process includes fabrication of a single damascene, dual damascene or other contact opening structure on a substrate; optionally pre-cleaning the structure typically using nitrogen or hydrogen plasma; depositing a thin metal barrier layer on the sidewalls and bottom of the structure; and redistributing or re-sputtering the barrier layer on the bottom and sidewalls of the structure.

Abstract translation: 一种用于在单个镶嵌，双镶嵌或其他接触开口结构上沉积阻挡层的新方法。 该方法消除了对结构的氩离子轰击的预清洁的需要，从而减少或消除了下面的导电层的表面的损伤和铜颗粒溅射到通孔或其他接触开口侧壁。 该方法包括在基底上制造单个镶嵌，双镶嵌或其它接触开口结构; 可以任选地预先使用氮或氢等离子体对结构进行预清洗; 在结构的侧壁和底部上沉积薄金属阻挡层; 并且在结构的底部和侧壁上重新分布或重新溅射阻挡层。