公开(公告)号：US08000137B2

公开(公告)日：2011-08-16

申请号：US12400015

申请日：2009-03-09

申请人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

发明人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

IPC分类号： G11C16/04

CPC分类号： G11C16/045 ,  G11C16/0441 ,  G11C16/12 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/11558

摘要： A nonvolatile semiconductor memory device includes a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

摘要翻译： 非易失性半导体存储器件包括第一PMOS晶体管和具有栅极的第二PMOS晶体管，第一和第二PMOS晶体管串联连接; 以及具有栅极的第一NMOS晶体管和第二NMOS晶体管，所述第一和第二NMOS晶体管串联连接; 其中第二PMOS晶体管的栅极和第二NMOS晶体管的栅极共同连接和浮置。

公开(公告)号：US07701778B2

公开(公告)日：2010-04-20

申请号：US11684035

申请日：2007-03-09

申请人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

发明人： Natsuo Ajika ,  Shoji Shukuri ,  Masaaki Mihara ,  Yoshiki Kawajiri

IPC分类号： G11C11/34

CPC分类号： G11C16/3436

摘要： The present invention relates to a nonvolatile semiconductor memory, and more specifically relates to a nonvolatile semiconductor memory with increased program throughput. The present invention provides a nonvolatile semiconductor memory device with a plurality of block source lines corresponding to the memory blocks, arranged in parallel to the word lines, a plurality of global source lines arranged in perpendicular to the block source lines; and a plurality of switches for selectively connecting corresponding ones of the block source lines and the global source lines.

摘要翻译： 非易失性半导体存储器技术领域本发明涉及一种非易失性半导体存储器，更具体地涉及一种具有增加的程序吞吐量的非易失性半导体存储器。 本发明提供了一种非易失性半导体存储器件，具有对应于与字线平行布置的存储块的多个块源极线，与块源极线垂直的多个全局源极线; 以及用于选择性地连接块源极线和全局源极线中的对应的多个开关。

公开(公告)号：US20090244972A1

公开(公告)日：2009-10-01

申请号：US12400015

申请日：2009-03-09

申请人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

发明人： Taku Ogura ,  Natsuo Ajika ,  Shoji Shukuri ,  Satoshi Shimizu ,  Yoshiki Kawajiri ,  Masaaki Mihara

IPC分类号： G11C14/00 ,  G11C16/04 ,  G11C7/06

CPC分类号： G11C16/045 ,  G11C16/0441 ,  G11C16/12 ,  G11C2216/10 ,  H01L27/11521 ,  H01L27/11558

摘要： A nonvolatile semiconductor memory device comprises a first PMOS transistor and a second PMOS transistor having a gate, the first and the second PMOS transistors being connected in series; and a first NMOS transistor and a second NMOS transistor having a gate, the first and the second NMOS transistors being connected in series; wherein the gate of the second PMOS transistor and the gate of the second NMOS transistor are commonly connected and floated.

摘要翻译： 非易失性半导体存储器件包括第一PMOS晶体管和具有栅极的第二PMOS晶体管，第一和第二PMOS晶体管串联连接; 以及具有栅极的第一NMOS晶体管和第二NMOS晶体管，所述第一和第二NMOS晶体管串联连接; 其中第二PMOS晶体管的栅极和第二NMOS晶体管的栅极共同连接和浮置。

公开(公告)号：US20070190724A1

公开(公告)日：2007-08-16

申请号：US11690704

申请日：2007-03-23

申请人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

发明人： Yasuyoshi Itoh ,  Shuuichi Ueno ,  Haruo Furuta ,  Natsuo Ajika

IPC分类号： H01L21/336

CPC分类号： H01L29/66833 ,  H01L21/26586 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/40117 ,  H01L29/42352 ,  H01L29/42368 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66583 ,  H01L29/7833 ,  H01L29/7923

摘要： It is an object to provide a semiconductor device capable of holding multibit information in one memory cell also when scaling for a nonvolatile memory progresses, and a method of manufacturing the semiconductor device. A trench (TRI) is formed in a channel portion of an MONOS transistor. Then, a source side portion and a drain side portion in a silicon nitride film (122) of a gate insulating film (120) which interpose the trench (TR1) are caused to function as first and second electric charge holding portions capable of holding electric charges (CH1) and (CH2). In the case in which the electric charges (CH1) are trapped and the electric charges (CH2) are then trapped, thus, a portion (130a) of a gate electrode (130) in the trench (TR1) functions as a shield. If a fixed potential is given to the gate electrode (130), the second electric charge holding portion is not influenced by an electric field (EF1) induced by the electric charges (CH1) so that the trapping of the electric charges (CH2) is not inhibited.

摘要翻译： 本发明的目的是提供一种能够在非易失性存储器的缩放进行时能够在一个存储单元中保持多位信息的半导体器件，以及半导体器件的制造方法。 在MONOS晶体管的沟道部分中形成沟槽（TRI）。 然后，使位于沟槽（TR1）的栅极绝缘膜（120）的氮化硅膜（122）中的源极侧部分和漏极侧部分作为能够保持的第一和第二电荷保持部 电荷（CH 1）和（CH 2）。 在电荷（CH 1）被捕获并且电荷（CH 2）然后被捕获的情况下，因此，沟槽（TR 1）中的栅电极（130）的部分（130a）用作 一个盾牌 如果向栅电极（130）施加固定电位，则第二电荷保持部不受电荷（CH 1）引起的电场（EF 1）的影响，使得电荷（CH 2）不被抑制。

公开(公告)号：US06611459B2

公开(公告)日：2003-08-26

申请号：US10164625

申请日：2002-06-10

申请人： Tatsuya Shiromoto ,  Natsuo Ajika ,  Satoshi Shimizu

发明人： Tatsuya Shiromoto ,  Natsuo Ajika ,  Satoshi Shimizu

IPC分类号： G11C1604

CPC分类号： H01L27/11526 ,  G11C11/005 ,  G11C16/0416 ,  H01L27/105 ,  H01L27/11543

摘要： A non-volatile semiconductor memory device usable in relatively wide applications and a method of manufacturing the same are provided. A NOR-type flash memory region (2) including a NOR-type memory cell transistor and a DINOR-type flash memory region (3) including a DINOR-type memory cell transistor are manufactured into a single semiconductor chip (1). A peripheral circuit region (7) including a transistor for a peripheral circuit or the like is manufactured into a region surrounding the NOR-type flash memory region (2) and the DINOR-type flash memory region (3). The peripheral circuit region (7) is shareable between the NOR-type flash memory region (2) and the DINOR-type flash memory region (3) by electrical connection to both of the regions.

摘要翻译： 提供了可用于相对广泛的应用的非易失性半导体存储器件及其制造方法。 包括NOR型存储单元晶体管和包括DINOR型存储单元晶体管的DINOR型闪存区域（3）的NOR型闪存区域（2）被制造成单个半导体芯片（1）。 包括用于外围电路等的晶体管的外围电路区域（7）被制造成围绕NOR型闪存区域（2）和DINOR型闪存区域（3）的区域。 外部电路区域（7）可通过电气连接到两个区域而在NOR型闪存区域（2）和DINOR型闪存区域（3）之间共享。

公开(公告)号：US5994733A

公开(公告)日：1999-11-30

申请号：US3641

申请日：1998-01-07

申请人： Naho Nishioka ,  Natsuo Ajika ,  Hiroshi Onoda

发明人： Naho Nishioka ,  Natsuo Ajika ,  Hiroshi Onoda

IPC分类号： H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L29/94

CPC分类号： H01L27/11526 ,  H01L27/115 ,  H01L27/11546

摘要： Each nonvolatile transistor comprises a floating gate electrode, an ONO film and a control gate electrode. An upper surface of a silicon oxide film is positioned at a height between upper and lower surfaces of the floating gate electrode. The control gate electrode continuously extends on the floating gate electrode and the silicon oxide film in a prescribed arrangement direction.

摘要翻译： 每个非易失性晶体管包括浮栅电极，ONO膜和控制栅电极。 氧化硅膜的上表面位于浮栅电极的上表面和下表面之间的高度处。 控制栅电极在规定的布置方向上在浮栅和氧化硅膜上连续地延伸。

公开(公告)号：US5672533A

公开(公告)日：1997-09-30

申请号：US555414

申请日：1995-11-09

申请人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

发明人： Hideaki Arima ,  Makoto Ohi ,  Natsuo Ajika ,  Atsushi Hachisuka ,  Tomonori Okudaira

IPC分类号： H01L21/8242 ,  H01L29/68 ,  H01L29/76 ,  H01L29/78 ,  H01L29/92 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： H01L29/7835 ,  H01L27/1085 ,  H01L27/10891 ,  H01L27/10894 ,  H01L29/66659

摘要： Disclosed is a semiconductor memory device in which defects in crystal in a junction region between a capacitor and a source/drain region, and a short channel effect of a transistor can be effectively reduced. The semiconductor memory device includes, on the side of a gate electrode at which the capacitor is connected, a sidewall formed to have a width larger than that of a sidewall on the side of a bit line, and a source/drain region to which the capacitor is connected and which is formed to have a diffusion depth larger than that of the opposite source/drain region. Therefore, the source/drain region effectively prevents defects in crystal from being produced in the junction region between the capacitor and the source/drain region connected to the capacitor and the sidewall effectively reduces the short channel effect.

摘要翻译： 公开了一种半导体存储器件，其中可以有效地减少电容器和源极/漏极区域之间的结区中的晶体缺陷和晶体管的短沟道效应。 半导体存储器件包括在电容器连接的栅电极侧，形成为具有比位线侧的侧壁宽度大的侧壁以及源极/漏极区， 电容器被连接并且被形成为具有比相对的源极/漏极区的扩散深度更大的扩散深度。 因此，源极/漏极区域有效地防止在电容器和连接到电容器的源极/漏极区域之间的结区域中产生晶体缺陷，并且侧壁有效地降低了短沟道效应。

公开(公告)号：US5600164A

公开(公告)日：1997-02-04

申请号：US536300

申请日：1995-09-29

申请人： Natsuo Ajika ,  Masahiro Hatanaka

发明人： Natsuo Ajika ,  Masahiro Hatanaka

IPC分类号： G11C17/00 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/105 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L27/02 ,  H01L29/78

CPC分类号： H01L27/105

摘要： An object of the present invention is to achieve an improved flash memory which enables to simultaneously obtain high performance and reliability even with voltage V.sub.CC of 3.3 V or below. The device includes a memory cell 6, a V.sub.CC type transistor 7 and a V.sub.PP type transistor 8. Memory cell 6 includes a tunnel oxide film 2, a floating gate 3 and a control gate 4. A V.sub.CC type transistor 7 includes a first gate insulating film 9 and a first gate 10. A V.sub.PP type transistor 8 includes a second gate insulating film 11 and a second gate 12. An inequality, t(V.sub.CC)

摘要翻译： 本发明的目的是实现一种改进的闪速存储器，即使在3.3V或更低的电压VCC下也能够同时获得高性能和可靠性。 该器件包括存储单元6，VCC型晶体管7和VPP型晶体管8.存储单元6包括隧道氧化物膜2，浮置栅极3和控制栅极4. VCC型晶体管7包括第一栅极绝缘 薄膜9和第一栅极10.PVP型晶体管8包括第二栅极绝缘膜11和第二栅极12.不等式t（VCC）

公开(公告)号：US5597755A

公开(公告)日：1997-01-28

申请号：US457193

申请日：1995-06-01

申请人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

发明人： Natsuo Ajika ,  Hideaki Arima ,  Atsushi Hachisuka

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108 ,  H01L21/70 ,  H01L27/00

CPC分类号： H01L27/10817 ,  H01L27/10852

摘要： A method of manufacturing a semiconductor memory device having stacked capacitors is disclosed. After forming a capacitor isolating layer on an insulation layer and forming a contact hole in the insulation layer, a first conductive layer is formed on the insulating layer and the capacitor isolating layer and on an inner surface of the contact hole. The first conductive layer is partially etched and removed by using an etch-back technique to be isolated into a first capacitor portion and a second capacitor portion. A dielectric layer is formed on the first conductive layer. A second conductive layer is formed on the dielectric layer.

摘要翻译： 公开了一种制造具有层叠电容器的半导体存储器件的方法。 在绝缘层上形成电容器隔离层并在绝缘层中形成接触孔之后，在绝缘层和电容器隔离层上以及接触孔的内表面上形成第一导电层。 通过使用蚀刻技术将第一导电层部分地蚀刻和去除，以将其隔离成第一电容器部分和第二电容器部分。 在第一导电层上形成电介质层。 在介电层上形成第二导电层。

公开(公告)号：US5504376A

公开(公告)日：1996-04-02

申请号：US222502

申请日：1994-04-04

申请人： Kazuyuki Sugahara ,  Natsuo Ajika ,  Toshiaki Ogawa ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

发明人： Kazuyuki Sugahara ,  Natsuo Ajika ,  Toshiaki Ogawa ,  Toshiaki Iwamatsu ,  Takashi Ipposhi

IPC分类号： H01L27/00 ,  H01L21/02 ,  H01L21/20 ,  H01L21/762 ,  H01L21/822 ,  H01L27/12 ,  H01L29/78 ,  H01L29/786 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L21/2007 ,  H01L21/76251 ,  H01L21/8221 ,  H01L2224/80357 ,  H01L2224/80895 ,  H01L2224/80896

摘要： In a method of manufacturing a stacked-type semiconductor device, firstly, a first semiconductor substrate having a first device formed thereon is covered with an interlayer insulating layer and a planarized polycrystalline silicon layer is formed on the interlayer insulating layer. The first semiconductor substrate and a second semiconductor substrate are joined together by putting the surface of the polycrystalline silicon layer in close contact with the surface of a refractory metal layer formed on the second semiconductor substrate, applying thermal treatment at 700.degree. C. or below and changing the refractory metal layer to silicide.

摘要翻译： 在叠层型半导体器件的制造方法中，首先，在层间绝缘层上形成有具有形成在其上的第一器件的第一半导体衬底，层间绝缘层形成平坦化的多晶硅层。 将第一半导体衬底和第二半导体衬底通过将多晶硅层的表面与形成在第二半导体衬底上的难熔金属层的表面紧密接触，在700℃以下进行热处理， 将难熔金属层改为硅化物。