公开(公告)号：US20100315760A1

公开(公告)日：2010-12-16

申请号：US12483474

申请日：2009-06-12

申请人： Rishikesh Krishnan ,  John Smythe ,  Vishwanath Bhat ,  Noel Rocklein ,  Bhaskar Srinivasan ,  Jeff Hully ,  Chris Carlson

发明人： Rishikesh Krishnan ,  John Smythe ,  Vishwanath Bhat ,  Noel Rocklein ,  Bhaskar Srinivasan ,  Jeff Hully ,  Chris Carlson

IPC分类号： H01G4/10

CPC分类号： H01L28/56 ,  H01G4/10 ,  H01L27/108

摘要： Capacitors and methods of forming capacitors are disclosed, and which include an inner conductive metal capacitor electrode and an outer conductive metal capacitor electrode. A capacitor dielectric region is received between the inner and the outer conductive metal capacitor electrodes and has a thickness no greater than 150 Angstroms. Various combinations of materials of thicknesses and relationships relative one another are disclosed which enables and results in the dielectric region having a dielectric constant k of at least 35 yet leakage current no greater than 1×10−7 amps/cm2 at from −1.1V to +1.1V.

摘要翻译： 公开了形成电容器的电容器和方法，其包括内部导电金属电容器电极和外部导电金属电容器电极。 电容器电介质区域被容纳在内导电金属电容电极和外导电金属电容器电极之间，并且具有不大于150埃的厚度。 公开了厚度和关系的材料的各种组合，其相互之间可以实现和导致电介质区域的介电常数k至少为35，而在-1.1V至-1.0V的范围内漏电流不大于1×10-7Aps / cm 2 + 1.1V。

公开(公告)号：US20100258903A1

公开(公告)日：2010-10-14

申请号：US12421916

申请日：2009-04-10

申请人： Bhaskar Srinivasan ,  Vassil Antonov ,  John Smythe

发明人： Bhaskar Srinivasan ,  Vassil Antonov ,  John Smythe

IPC分类号： H01L27/10 ,  B05D5/12

CPC分类号： H01L28/75 ,  C23C16/404 ,  C23C16/409 ,  C23C16/45527 ,  C23C16/45529 ,  C23C16/45531 ,  C23C16/56 ,  H01G4/33 ,  H01L21/02197 ,  H01L21/022 ,  H01L21/0228 ,  H01L28/56 ,  H01L28/65

摘要： Strontium ruthenium oxide provides an effective interface between a ruthenium conductor and a strontium titanium oxide dielectric. Formation of the strontium ruthenium oxide includes the use of atomic layer deposition to form strontium oxide and subsequent annealing of the strontium oxide to form the strontium ruthenium oxide. A first atomic layer deposition of strontium oxide is preformed using water as an oxygen source, followed by a subsequent atomic layer deposition of strontium oxide using ozone as an oxygen source.

摘要翻译： 钌氧化钌提供钌导体和锶钛氧化物电介质之间的有效界面。 锶氧化钌的形成包括使用原子层沉积形成氧化锶，随后退火氧化锶以形成氧化锶锶。 使用水作为氧源来进行氧化锶的第一原子层沉积，然后使用臭氧作为氧源，随后用氧化锶沉积氧化锶。

公开(公告)号：US20080194088A1

公开(公告)日：2008-08-14

申请号：US11705992

申请日：2007-02-14

申请人： Bhaskar Srinivasan ,  John Smythe

发明人： Bhaskar Srinivasan ,  John Smythe

IPC分类号： H01L21/20 ,  C23C16/00

CPC分类号： C23C16/405 ,  C23C16/409 ,  C23C16/45529 ,  C23C16/45531 ,  H01G4/085 ,  H01G4/1227 ,  H01L21/02186 ,  H01L21/022 ,  H01L21/0228 ,  H01L21/3141 ,  H01L21/31604 ,  H01L21/31691

摘要： Atomic layer deposition methods as described herein can be advantageously used to form a metal-containing layer on a substrate. For example, certain methods as described herein can form a strontium titanate layer that has low carbon content (e.g., low strontium carbonate content), which can result in layer with a high dielectric constant.

摘要翻译： 本文所述的原子层沉积方法可有利地用于在基底上形成含金属的层。 例如，如本文所述的某些方法可以形成具有低碳含量（例如低碳酸锶含量）的钛酸锶层，其可导致具有高介电常数的层。

公开(公告)号：US08461060B2

公开(公告)日：2013-06-11

申请号：US13616080

申请日：2012-09-14

申请人： Nishant Sinha ,  Gurtej Sandhu ,  Neil Greeley ,  John Smythe

发明人： Nishant Sinha ,  Gurtej Sandhu ,  Neil Greeley ,  John Smythe

IPC分类号： H01L21/31

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.

摘要翻译： 公开了半导体器件及其形成方法，其中至少两个相邻的导体在它们之间具有空隙绝缘体，其被绝缘材料的纳米颗粒覆盖，其尺寸是防止纳米颗粒基本上进入气隙的尺寸。

公开(公告)号：US08349545B2

公开(公告)日：2013-01-08

申请号：US13369208

申请日：2012-02-08

申请人： Scott Sills ,  Gurtej Sandhu ,  John Smythe ,  Ming Zhang

发明人： Scott Sills ,  Gurtej Sandhu ,  John Smythe ,  Ming Zhang

IPC分类号： G03F7/26

CPC分类号： H01L21/0274 ,  G03F7/20 ,  G03F7/40 ,  H01L21/0337 ,  H01L21/0338

摘要： Some embodiments include methods of forming patterns of openings. The methods may include forming spaced features over a substrate. The features may have tops and may have sidewalls extending downwardly from the tops. A first material may be formed along the tops and sidewalls of the features. The first material may be formed by spin-casting a conformal layer of the first material across the features, or by selective deposition along the features relative to the substrate. After the first material is formed, fill material may be provided between the features while leaving regions of the first material exposed. The exposed regions of the first material may then be selectively removed relative to both the fill material and the features to create the pattern of openings.

公开(公告)号：US20120258599A1

公开(公告)日：2012-10-11

申请号：US13526792

申请日：2012-06-19

申请人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

发明人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

IPC分类号： H01L21/311

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Methods are disclosed, including for increasing the density of isolated features in an integrated circuit. Also disclosed are associated structures. In some embodiments, contacts are formed on pitch with other structures, such as conductive interconnects that may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. Features in the selectively definable material are trimmed, and spacer material is blanket deposited over the features and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed, leaving a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

摘要翻译： 公开了包括用于增加集成电路中的隔离特征的密度的方法。 还公开了相关联的结构。 在一些实施例中，触点是与其他结构形成的，例如可以由间距倍增形成的导电互连。 为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。 在可选择定义的材料中的特征被修整，并且间隔物材料被毯子沉积在特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。 去除可选择定义的材料，留下由间隔物材料限定的掩模。 由间隔物材料限定的图案可以转移到基底上，以形成间距接触。 在一些实施例中，上电触点可用于电接触衬底中的导电互连。

公开(公告)号：US07952174B2

公开(公告)日：2011-05-31

申请号：US12473849

申请日：2009-05-28

申请人： Nishant Sinha ,  Gurtej Sandhu ,  Neil Greeley ,  John Smythe

发明人： Nishant Sinha ,  Gurtej Sandhu ,  Neil Greeley ,  John Smythe

IPC分类号： H01L23/58

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.

摘要翻译： 公开了半导体器件及其形成方法，其中至少两个相邻的导体在它们之间具有空隙绝缘体，其被绝缘材料的纳米颗粒覆盖，其尺寸是防止纳米颗粒基本上进入气隙的尺寸。

公开(公告)号：US20110057161A1

公开(公告)日：2011-03-10

申请号：US12557315

申请日：2009-09-10

申请人： Gurtej Sandhu ,  John Smythe ,  Jun Liu

发明人： Gurtej Sandhu ,  John Smythe ,  Jun Liu

IPC分类号： H01L47/00 ,  H01L21/06

CPC分类号： H01L45/06 ,  G11C13/0004 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1293 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148 ,  H01L45/1683

摘要： Various embodiments described herein provide a memory device including a variable resistance material having a thermally isolating and electrically conductive isolation region arranged between the variable resistance material and an electrode to allow for efficient heating of the variable resistance material by a programming current. An electrically and thermally isolating isolation region may be arranged around the variable resistance material.

摘要翻译： 本文描述的各种实施例提供了一种包括可变电阻材料的存储器件，该可变电阻材料具有布置在可变电阻材料和电极之间的隔热和导电隔离区域，以允许通过编程电流有效地加热可变电阻材料。 可以在可变电阻材料周围布置电隔离隔离区域。

公开(公告)号：US20100301462A1

公开(公告)日：2010-12-02

申请号：US12473849

申请日：2009-05-28

申请人： Nishant Sinha ,  Gurtej Sandhu ,  Neil Greeley ,  John Smythe

发明人： Nishant Sinha ,  Gurtej Sandhu ,  Neil Greeley ,  John Smythe

IPC分类号： H01L23/522 ,  H01L21/31

CPC分类号： H01L23/5222 ,  H01L21/7682 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device and a method of forming it are disclosed in which at least two adjacent conductors have an air-gap insulator between them which is covered by nanoparticles of insulating material being a size which prevent the nanoparticles from substantially entering into the air-gap.

摘要翻译： 公开了半导体器件及其形成方法，其中至少两个相邻的导体在它们之间具有空隙绝缘体，其被绝缘材料的纳米颗粒覆盖，其尺寸是防止纳米颗粒基本上进入气隙的尺寸。

公开(公告)号：US07737039B2

公开(公告)日：2010-06-15

申请号：US11933664

申请日：2007-11-01

申请人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

发明人： Gurtej Sandhu ,  Mark Kiehlbauch ,  Steve Kramer ,  John Smythe

IPC分类号： H01L21/311

CPC分类号： H01L21/76816 ,  H01L21/0337 ,  H01L21/0338 ,  H01L23/528 ,  H01L2924/0002 ,  Y10S438/942 ,  H01L2924/00

摘要： Methods are disclosed, such as those involving increasing the density of isolated features in an integrated circuit. Also disclosed are structures associated with the methods. In one or more embodiments, contacts are formed on pitch with other structures, such as conductive interconnects. The interconnects may be formed by pitch multiplication. To form the contacts, in some embodiments, a pattern corresponding to some of the contacts is formed in a selectively definable material such as photoresist. The features in the selectively definable material are trimmed to desired dimensions. Spacer material is blanket deposited over the features in the selectively definable material and the deposited material is then etched to leave spacers on sides of the features. The selectively definable material is removed to leave a mask defined by the spacer material. The pattern defined by the spacer material may be transferred to a substrate, to form on pitch contacts. In some embodiments, the on pitch contacts may be used to electrically contact conductive interconnects in the substrate.

摘要翻译： 公开了诸如涉及增加集成电路中的隔离特征的密度的方法。 还公开了与该方法相关联的结构。 在一个或多个实施例中，触头在其它结构（例如导电互连）的间距上形成。 互连可以由间距倍增形成。 为了形成触点，在一些实施例中，对应于一些触点的图案形成在诸如光致抗蚀剂的可选择定义的材料中。 可选择定义的材料中的特征被修剪到期望的尺寸。 间隔材料被毯子沉积在可选择定义的材料中的特征上，然后蚀刻沉积的材料以在特征的侧面留下间隔物。 去除可选择定义的材料以留下由间隔物材料限定的掩模。 由间隔物材料限定的图案可以转移到基底上，以形成间距接触。 在一些实施例中，上电触点可用于电接触衬底中的导电互连。