公开(公告)号：US06133121A

公开(公告)日：2000-10-17

申请号：US950913

申请日：1997-10-15

申请人： Yoshitaka Tsunashima ,  Katsuya Okumura ,  Shigeru Yonemoto

发明人： Yoshitaka Tsunashima ,  Katsuya Okumura ,  Shigeru Yonemoto

IPC分类号： C23C16/458 ,  H01L21/31 ,  H01L21/324 ,  H01L21/673 ,  C23C16/00

CPC分类号： H01L21/67303 ,  C23C16/4583 ,  H01L21/67306 ,  H01L21/67309

摘要： A plurality of rods are arranged between first and second plates. A plurality of support members formed of heat-resistant strings, for example, SiC are stretched between the rods and wafers are supported by the support members. The wafers are separated from the rods while they are supported on the support members.

摘要翻译： 多个杆布置在第一和第二板之间。 由耐热线圈例如SiC形成的多个支撑构件在杆之间拉伸，并且晶片由支撑构件支撑。 当晶片被支撑在支撑构件上时，晶片与棒分离。

公开(公告)号：US6091117A

公开(公告)日：2000-07-18

申请号：US373558

申请日：1999-08-13

申请人： Jun-ichi Shiozawa ,  Yoshitaka Tsunashima ,  Katsuya Okumura

发明人： Jun-ichi Shiozawa ,  Yoshitaka Tsunashima ,  Katsuya Okumura

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L29/08

CPC分类号： H01L29/66628 ,  H01L21/76895 ,  H01L29/0847

摘要： A field effect transistor is manufactured by forming an isolating structure on a semiconductor substrate to define an active area. A gate structure is formed which is insulated from a surface of the active area of the semiconductor substrate. An amorphous silicon film is formed on the gate structure, on the surface of the semiconductor substrate, and on the isolating structure. A first portion of the amorphous silicon film is converted to an epitaxial film and a second portion of the amorphous silicon film is converted to a polysilicon film. Impurities are diffused throughout the polysilicon film and into an upper surface portion of said epitaxial film. The impurity doped polysilicon film and the upper surface portion of the epitaxial film are oxidized to form oxide films and the oxide films are removed so that the epitaxial film remains at least on the active area of the semiconductor substrate. Source and drain regions of the transistor are formed in the active area of the semiconductor substrate.

摘要翻译： 通过在半导体衬底上形成隔离结构来限定有源区域来制造场效应晶体管。 形成与半导体衬底的有源区的表面绝缘的栅极结构。 在栅极结构，半导体衬底的表面和隔离结构上形成非晶硅膜。 将非晶硅膜的第一部分转变为外延膜，将非晶硅膜的第二部分转换为多晶硅膜。 杂质扩散到整个多晶硅膜并进入所述外延膜的上表面部分。 杂质掺杂多晶硅膜和外延膜的上表面部分被氧化以形成氧化物膜，并且去除氧化物膜，使得外延膜至少保留在半导体衬底的有源区上。 晶体管的源区和漏区形成在半导体衬底的有源区中。

公开(公告)号：US5970352A

公开(公告)日：1999-10-19

申请号：US64716

申请日：1998-04-23

申请人： Jun-ichi Shiozawa ,  Yoshitaka Tsunashima ,  Katsuya Okumura

发明人： Jun-ichi Shiozawa ,  Yoshitaka Tsunashima ,  Katsuya Okumura

IPC分类号： H01L29/78 ,  H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/768 ,  H01L29/08

CPC分类号： H01L29/66628 ,  H01L21/76895 ,  H01L29/0847

摘要： A field effect transistor is manufactured by forming an isolating structure on a semiconductor substrate to define an active area. A gate structure is formed which is insulated from a surface of the active area of the semiconductor substrate. An amorphous silicon film is formed on the gate structure, on the surface of the semiconductor substrate, and on the isolating structure. A first portion of the amorphous silicon film is converted to an epitaxial film and a second portion of the amorphous silicon film is converted to a polysilicon film. Impurities are diffused throughout the polysilicon film and into an upper surface portion of said epitaxial film. The impurity doped polysilicon film and the upper surface portion of the epitaxial film are oxidized to form oxide films and the oxide films are removed so that the epitaxial film remains at least on the active area of the semiconductor substrate. Source and drain regions of the transistor are formed in the active area of the semiconductor substrate.

摘要翻译： 通过在半导体衬底上形成隔离结构来限定有源区域来制造场效应晶体管。 形成与半导体衬底的有源区的表面绝缘的栅极结构。 在栅极结构，半导体衬底的表面和隔离结构上形成非晶硅膜。 将非晶硅膜的第一部分转变为外延膜，将非晶硅膜的第二部分转换为多晶硅膜。 杂质扩散到整个多晶硅膜并进入所述外延膜的上表面部分。 杂质掺杂多晶硅膜和外延膜的上表面部分被氧化以形成氧化物膜，并且去除氧化物膜，使得外延膜至少保留在半导体衬底的有源区上。 晶体管的源区和漏区形成在半导体衬底的有源区中。

公开(公告)号：US5605574A

公开(公告)日：1997-02-25

申请号：US530641

申请日：1995-09-20

申请人： Yoshitaka Tsunashima ,  Katsuya Okumura

发明人： Yoshitaka Tsunashima ,  Katsuya Okumura

IPC分类号： H01L21/683 ,  C01B31/36 ,  C23C16/458 ,  C30B25/12 ,  C30B31/14 ,  F16F1/02 ,  H01L21/673 ,  C23C16/00

CPC分类号： H01L21/67309 ,  C23C16/4583 ,  C30B25/12 ,  C30B31/14

摘要： The wafer support apparatus and method provide a plurality of elastic supports having a smooth curvature for contacting a wafer at a respective plurality of support points. Each elastic support directly contacts the wafer at a support point and expands and/or compresses independently of the other elastic supports to accommodate the bending of the wafer during processing.A wafer support apparatus includes a plurality of flexible elastic supports onto which a wafer is directly positioned, wherein each of the plurality of elastic supports holds the wafer during processing by compressing or expanding in response to bending of the wafer during processing to provide continuous even support for the wafer during processing. A wafer support method includes the steps of providing a plurality of flexible elastic supports and positioning a wafer to be processed directly on the plurality of elastic supports, wherein each of the plurality of elastic supports holds the wafer during processing by compressing or expanding in response to bending of the wafer during processing to provide continuous even support for the wafer during processing.The elastic supports may be manufactured using a method including the steps of providing a mold in the shape of a wafer elastic support; depositing a layer of an elastic material having low thermal expansion coefficient on the mold; forming a hole in the deposited layer of elastic material at the base of the mold; and burning out the mold.

摘要翻译： 晶片支撑装置和方法提供了多个具有平滑曲率的弹性支撑件，用于在相应的多个支撑点处接触晶片。 每个弹性支撑件在支撑点处直接接触晶片并且独立于其它弹性支撑件膨胀和/或压缩以适应处理期间晶片的弯曲。 晶片支撑装置包括多个柔性弹性支撑件，晶片直接定位在该多个柔性弹性支撑件上，其中多个弹性支撑件中的每一个在处理期间通过在处理期间响应于晶片的弯曲而压缩或膨胀来保持晶片以提供连续的均匀支撑 用于处理过程中的晶圆。 一种晶片支撑方法包括以下步骤：提供多个柔性弹性支撑件并将待加工的晶片直接定位在所述多个弹性支撑件上，其中所述多个弹性支撑件中的每个弹性支撑件在处理期间通过压缩或扩张来响应于 在处理期间晶片的弯曲以在处理期间为晶片提供连续的均匀支撑。 可以使用包括以下步骤的方法制造弹性支撑件：提供具有晶片弹性支撑件形状的模具; 在模具上沉积具有低热膨胀系数的弹性材料层; 在模具底部的弹性材料的沉积层中形成孔; 并焚烧模具。

公开(公告)号：US5485034A

公开(公告)日：1996-01-16

申请号：US344694

申请日：1994-11-18

申请人： Takeo Maeda ,  Hiroshi Gojohbori ,  Yoshitaka Tsunashima

发明人： Takeo Maeda ,  Hiroshi Gojohbori ,  Yoshitaka Tsunashima

IPC分类号： H01L29/73 ,  H01L21/331 ,  H01L27/06 ,  H01L29/10 ,  H01L29/732 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/7322 ,  H01L27/0623 ,  H01L29/1004

摘要： A semiconductor device of this invention includes an N-type semiconductor region functioning as a collector of a bipolar transistor, a silicon dioxide film doped with boron and formed in contact with the surface of the N-type semiconductor region, a P-type semiconductor region formed in contact with the silicon dioxide film doped with boron in the N-type semiconductor region and functioning as a base of the bipolar transistor, and an N-type semiconductor region formed in the P-type semiconductor region and functioning as an emitter of the bipolar transistor.

摘要翻译： 本发明的半导体器件包括用作双极晶体管的集电极的N型半导体区域，掺杂有硼并与N型半导体区域的表面接触形成的二氧化硅膜，P型半导体区域 形成为与N型半导体区域中掺杂有硼的二氧化硅膜接触并用作双极晶体管的基极，并且形成在P型半导体区域中并用作发光体的N型半导体区域 双极晶体管。

公开(公告)号：US07972960B1

公开(公告)日：2011-07-05

申请号：US12886240

申请日：2010-09-20

申请人： Kyoichi Suguro ,  Yoshitaka Tsunashima

发明人： Kyoichi Suguro ,  Yoshitaka Tsunashima

IPC分类号： H01L21/44

CPC分类号： H01L21/288 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02601 ,  H01L21/02628 ,  H01L21/02639 ,  H01L21/76877 ,  H01L21/76879 ,  H01L21/76883

摘要： A method for manufacturing a thin film includes: applying a liquid to a surface of a processing target member having at least one of a trench and a concave portion. The liquid includes a solvent and at least one of fine particles of a metal, fine particles of a semiconductor, fine particles containing a metal oxide, and fine particles containing a semiconductor oxide. A first heat treatment is included for volatilizing the solvent of the liquid applied to the surface of the processing target member. The fine particles are remained on the surface of the processing target member. A second heat treatment is also included for heating the fine particles by using microwave irradiation. At least one of the trench and the concave portion is filled with the thin film containing the fine particles or a component of the fine particles.

摘要翻译： 一种制造薄膜的方法包括：将液体施加到具有沟槽和凹部中的至少一个的处理目标构件的表面。 该液体包括溶剂和金属微粒，半导体微粒，含有金属氧化物的微粒和含有半导体氧化物的微粒中的至少一种。 包括第一次热处理以挥发施加到加工对象部件表面的液体的溶剂。 微粒保留在加工对象构件的表面上。 还包括通过使用微波照射来加热微粒的第二热处理。 沟槽和凹部中的至少一个填充有含有细颗粒或细颗粒成分的薄膜。

公开(公告)号：US07772671B2

公开(公告)日：2010-08-10

申请号：US12068635

申请日：2008-02-08

申请人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

发明人： Kyoichi Suguro ,  Kiyotaka Miyano ,  Ichiro Mizushima ,  Yoshitaka Tsunashima ,  Takayuki Hiraoka ,  Yasushi Akasaka ,  Tsunetoshi Arikado

IPC分类号： H01L29/00

CPC分类号： H01L21/28194 ,  H01L21/28088 ,  H01L21/28167 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/76262 ,  H01L21/823481 ,  H01L29/511 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66537 ,  H01L29/66545

摘要： A semiconductor device including a semiconductor substrate having on its surface a recess and at least one projection formed in the recess. The projection has a channel region and an element isolating insulating film is formed in the recess. A MIS type semiconductor element is formed on the semiconductor substrate and includes a gate electrode formed on the channel region of the projection via a gate insulating film. Source and drain regions are formed to pinch the channel region of the projection therebetween. A channel region of the MIS type semiconductor element is formed to reach the at least one projection located adjacent to the MIS type semiconductor element in its channel width direction via the recess. A top surface of the at least one projection is located higher than the top surface of the element isolating insulating film by 20 nm or more.

摘要翻译： 一种半导体器件，包括在其表面上具有凹部的半导体衬底和形成在凹部中的至少一个突起。 突起具有沟道区域，并且在凹部中形成元件隔离绝缘膜。 MIS半导体元件形成在半导体衬底上，并且包括通过栅极绝缘膜形成在突起的沟道区上的栅电极。 形成源区和漏区以夹住其间的突起的沟道区。 MIS型半导体元件的沟道区域形成为经由凹部在其沟道宽度方向上到达位于与MIS型半导体元件相邻的至少一个突起。 所述至少一个突起的顶表面比所述元件隔离绝缘膜的顶表面高20nm或更大。

公开(公告)号：US20080242115A1

公开(公告)日：2008-10-02

申请号：US11902300

申请日：2007-09-20

申请人： Kazuhiro Eguchi ,  Seiji Inumiya ,  Yoshitaka Tsunashima

发明人： Kazuhiro Eguchi ,  Seiji Inumiya ,  Yoshitaka Tsunashima

IPC分类号： H01L21/31

CPC分类号： H01L29/511 ,  C23C16/30 ,  C23C16/45523 ,  H01L21/28176 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/28229 ,  H01L21/31604 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/78

摘要： A semiconductor device comprising a semiconductor substrate, a gate dielectrics formed on the semiconductor substrate and including a silicon oxide film containing a metallic element, the silicon oxide film containing the metallic element including a first region near a lower surface thereof, a second region near an upper surface thereof, and a third region between the first and second regions, the metallic element contained in the silicon oxide film having a density distribution in a thickness direction of the silicon oxide film, a peak of the density distribution existing in the third region, and an electrode formed on the gate dielectrics.

摘要翻译： 一种半导体器件，包括半导体衬底，形成在所述半导体衬底上并包括含有金属元素的氧化硅膜的栅极电介质，所述氧化硅膜含有所述金属元素，所述金属元素包括在其下表面附近的第一区域， 上表面和第一和第二区域之间的第三区域，包含在氧化硅膜中的金属元素在氧化硅膜的厚度方向上具有密度分布，存在于第三区域中的密度分布的峰值， 以及形成在栅极电介质上的电极。

公开(公告)号：US20080211004A1

公开(公告)日：2008-09-04

申请号：US12040224

申请日：2008-02-29

申请人： Yoshio OZAWA ,  Ichiro Mizushima ,  Takashi Suzuki ,  Hirokazu Ishida ,  Yoshitaka Tsunashima

发明人： Yoshio OZAWA ,  Ichiro Mizushima ,  Takashi Suzuki ,  Hirokazu Ishida ,  Yoshitaka Tsunashima

IPC分类号： H01L29/32 ,  H01L21/20

CPC分类号： H01L29/788 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/04

摘要： A semiconductor device includes a silicon crystal layer on an insulating layer, the silicon crystal layer containing a crystal lattice mismatch plane, a memory cell array portion on the silicon crystal layer, the memory cell array portion including memory strings, each of the memory strings including nonvolatile memory cell transistors connected in series in a first direction, the memory strings being arranged in a second direction orthogonal to the first direction, the crystal lattice mismatch plane crossing the silicon crystal along the second direction without passing under gates of the nonvolatile memory cell transistors as viewed from a top of the silicon crystal layer, or crossing the silicon crystal along the first direction with passing under gates of the nonvolatile memory cell transistors as viewed from the top of the silicon crystal layer.

摘要翻译： 半导体器件包括绝缘层上的硅晶体层，含有晶格失配平面的硅晶体层，硅晶体层上的存储单元阵列部分，存储单元阵列部分包括存储器串，每个存储器串包括 所述非易失性存储单元晶体管沿第一方向串联连接，所述存储器串沿与所述第一方向正交的第二方向布置，所述晶格失配面沿着所述第二方向与所述硅晶体交叉，而不通过所述非易失性存储单元晶体管的栅极 从硅晶体层的顶部观察，或者从硅晶体层的顶部观察时沿着非易失性存储单元晶体管的栅极通过硅晶体沿第一方向。

公开(公告)号：US07306994B2

公开(公告)日：2007-12-11

申请号：US10915805

申请日：2004-08-11

申请人： Yoshitaka Tsunashima ,  Seiji Inumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

发明人： Yoshitaka Tsunashima ,  Seiji Inumiya ,  Yasumasa Suizu ,  Yoshio Ozawa ,  Kiyotaka Miyano ,  Masayuki Tanaka

IPC分类号： H01L21/8234

CPC分类号： H01L21/82345 ,  H01L21/28088 ,  H01L21/28185 ,  H01L21/28194 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/31604 ,  H01L21/823462 ,  H01L21/823475 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656

摘要： Claimed and disclosed is a semiconductor device including a transistor having a gate insulating film structure containing nitrogen or fluorine in a compound, such as metal silicate, containing metal, silicon and oxygen, a gate insulating film structure having a laminated structure of an amorphous metal oxide film and metal silicate film, or a gate insulating film structure having a first gate insulating film including an oxide film of a first metal element and a second gate insulating film including a metal silicate film of a second metal element.

摘要翻译： 权利要求和公开的是一种半导体器件，包括具有在包含金属，硅和氧的金属硅酸盐的化合物中含有氮或氟的栅极绝缘膜结构的晶体管，具有非晶态金属氧化物层叠结构的栅极绝缘膜结构 膜和金属硅酸盐膜，或具有包括第一金属元素的氧化物膜的第一栅极绝缘膜和包括第二金属元素的金属硅酸盐膜的第二栅极绝缘膜的栅极绝缘膜结构。