公开(公告)号：US09536805B2

公开(公告)日：2017-01-03

申请号：US14324072

申请日：2014-07-03

Applicant: QUALCOMM Incorporated

Inventor： Siamak Fazelpour ,  Jiantao Zheng ,  Mario Francisco Velez ,  Sun Yun ,  Rajneesh Kumar ,  Houssam Wafic Jomaa

IPC: H01L23/00 ,  H01L25/00 ,  H01L23/42 ,  H01L23/36 ,  H01L25/16 ,  H01L25/18 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538

CPC classification number: H01L23/42 ,  H01L23/36 ,  H01L23/49811 ,  H01L23/50 ,  H01L23/5385 ,  H01L25/16 ,  H01L25/18 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73253 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19106 ,  H01L2924/3511

Abstract: A hybrid package having a processor module disposed on a substrate and an auxiliary module disposed on a patterned lid. The auxiliary module may be a memory module, a power management integrated circuit (PMIC) module, and/or other suitable module, that are located in the package along with the processor module. Having the auxiliary module in the package with the processor module reduces the noise at the solder bump between the processor module and the substrate. Having the auxiliary module in the package with the processor module also allows other modules to be added to the package without increasing the area of the package.

Abstract translation: 一种具有设置在基板上的处理器模块和设置在图案化盖上的辅助模块的混合封装。 辅助模块可以是与处理器模块一起位于包装中的存储器模块，电源管理集成电路（PMIC）模块和/或其他合适的模块。 将处理器模块的封装中的辅助模块降低处理器模块和基板之间的焊料凸块处的噪音。 将包含处理器模块的辅助模块也允许将其他模块添加到包装中，而不增加包装的面积。

公开(公告)号：US09461008B2

公开(公告)日：2016-10-04

申请号：US13787444

申请日：2013-03-06

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar ,  Omar J. Bchir

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498 ,  H05K3/34 ,  H01L23/14

CPC classification number: H01L24/13 ,  H01L21/4867 ,  H01L23/147 ,  H01L23/49811 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0401 ,  H01L2224/05548 ,  H01L2224/1132 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/119 ,  H01L2224/13006 ,  H01L2224/13024 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/73204 ,  H01L2224/81193 ,  H01L2224/814 ,  H01L2224/81409 ,  H01L2224/81411 ,  H01L2224/81815 ,  H01L2224/94 ,  H01L2924/12042 ,  H05K3/3436 ,  H05K3/3468 ,  H05K3/3484 ,  H05K2201/10674 ,  Y02P70/613 ,  H01L2924/00012 ,  H01L2224/81 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2924/01047 ,  H01L2924/01029 ,  H01L2924/00

Abstract: A solder on trace device includes a conductive trace on a semiconductor substrate surface. The conductive trace has a sidewall and a bonding surface. The solder on trace device also includes a passivation layer on at least one end of the conductive trace. The solder on trace device further includes a pre-solder material on the sidewall and the bonding surface of the conductive trace.

Abstract translation: 迹线装置上的焊料包括在半导体衬底表面上的导电迹线。 导电迹线具有侧壁和接合表面。 跟踪装置上的焊料还包括在导电迹线的至少一端上的钝化层。 跟踪装置上的焊料还包括在侧壁上的预焊料材料和导电迹线的接合表面。

公开(公告)号：US09159670B2

公开(公告)日：2015-10-13

申请号：US14318490

申请日：2014-06-27

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Omar James Bchir

IPC: H01L21/4763 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L23/528 ,  H01L21/768 ,  H01L23/498 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/131 ,  H01L2224/14133 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H01L2924/3841 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/094 ,  Y02P70/611 ,  H01L2924/00014 ,  H01L2924/014

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect, a first cavity, and a second interconnect. The first dielectric layer includes first and second surfaces. The first interconnect is embedded in the first dielectric layer. The first interconnect includes a first side and a second side. The first side is surrounded by the first dielectric layer, where at least a part of the second side is free of contact with the first dielectric layer. The first cavity traverses the first surface of the first dielectric layer to the second side of the first interconnect, where the first cavity overlaps the first interconnect. The second interconnect includes a third side and a fourth side, where the third side is coupled to the first surface of the first dielectric layer.

Abstract translation: 一些新颖的特征涉及包括第一介电层，第一互连，第一腔和第二互连的衬底。 第一介电层包括第一和第二表面。 第一互连嵌入在第一电介质层中。 第一互连包括第一侧和第二侧。 第一侧被第一介电层包围，其中第二侧的至少一部分与第一介电层不接触。 第一空腔穿过第一介电层的第一表面到第一互连的第二侧，其中第一腔与第一互连重叠。 第二互连包括第三侧和第四侧，其中第三侧耦合到第一介电层的第一表面。

公开(公告)号：US09105626B2

公开(公告)日：2015-08-11

申请号：US13790728

申请日：2013-03-08

Applicant: QUALCOMM Incorporated

Inventor： Rajneesh Kumar

IPC: H01L23/498 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L23/49816 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L25/105 ,  H01L25/50 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/81192 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1432 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A bare-die first package includes a patterned insulating layer that exposes first package balls in vias. The vias enable a second package to be positioned on the first package in a proper ball-to-ball alignment without the need for flattening or coining.

Abstract translation: 裸裸裸片第一封装包括图案化绝缘层，其在通孔中暴露第一封装球。 通孔能够使第二包装以适当的球对球定位而定位在第一包装上，而不需要平整或压印。

公开(公告)号：US08772951B1

公开(公告)日：2014-07-08

申请号：US14014192

申请日：2013-08-29

Applicant: QUALCOMM Incorporated

Inventor： Chin-Kwan Kim ,  Rajneesh Kumar ,  Omar James Bchir

IPC: H01L21/4763 ,  H01L29/40

CPC classification number: H01L23/498 ,  H01L21/4857 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L24/06 ,  H01L24/16 ,  H01L24/17 ,  H01L24/81 ,  H01L2224/11 ,  H01L2224/14133 ,  H01L2224/16237 ,  H01L2224/16238 ,  H01L2224/17051 ,  H01L2224/81191 ,  H01L2224/81385 ,  H01L2224/81801 ,  H05K1/0296 ,  H05K1/111 ,  H05K3/4682 ,  H05K2201/0376 ,  H05K2201/09227

Abstract: Some novel features pertain to a substrate that includes a first dielectric layer, a first interconnect embedded in a first surface of the first dielectric layer, and a second interconnect on the first surface of the first dielectric layer. The first interconnect is offset from the first surface of the first dielectric layer. The first interconnect being offset towards an inner portion of the first dielectric layer. In some implementations, the substrate further includes a third interconnect embedded in the first surface of the first dielectric layer, and a fourth interconnect on the first surface of the first dielectric layer. The first interconnect and the second interconnect are adjacent interconnects. In some implementations, the substrate further includes a first pad on the first surface of the first dielectric layer. The first pad is coupled to the first interconnect.

Abstract translation: 一些新颖的特征涉及包括第一介电层，嵌入在第一介电层的第一表面中的第一互连以及在第一介电层的第一表面上的第二互连的衬底。 第一互连件与第一介电层的第一表面偏移。 第一互连件朝向第一介电层的内部部分偏移。 在一些实施方案中，衬底还包括嵌入在第一介电层的第一表面中的第三互连和在第一介电层的第一表面上的第四互连。 第一互连和第二互连是相邻的互连。 在一些实施方案中，衬底还包括在第一介电层的第一表面上的第一焊盘。 第一焊盘耦合到第一互连。