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    Memory component with error-detect-correct code interface
    31.
    发明授权
    Memory component with error-detect-correct code interface 有权

    公开(公告)号：US09823966B1

    公开(公告)日：2017-11-21

    申请号：US14527422

    申请日：2014-10-29

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware ,  Brent S. Haukness ,  Lawrence Lai

    IPC: G11C29/00 ,  G06F11/10

    CPC classification number: G06F11/1076 ,  G06F11/1048

    Abstract: A memory component internally generates and stores the check bits of error detect and correct code (EDC). In a first mode, during a read transaction, the check bits are sent to the memory controller along with the data on the data mask (DM) signal lines. In a second mode, an unmasked write transaction is defined where the check bits are sent to the memory component on the data mask signal lines. In a third mode, a masked write transaction is defined where at least a portion of the check bits are sent from the memory controller on the data signal lines coincident with an asserted data mask signal line. By sending the check bits along with the data, the EDC code can be used to detect and correct errors that occur between the memory component and the memory controller.

    SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE
    34.
    发明申请
    SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE 有权
    单指令，多列操作存储器件

    公开(公告)号：US20150178187A1

    公开(公告)日：2015-06-25

    申请号：US14637369

    申请日：2015-03-03

    Applicant: Rambus Inc.

    Inventor： Thomas Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

    IPC: G06F12/02

    CPC classification number: G06F12/023 ,  G06F2212/2024 ,  G11C7/1006 ,  G11C7/1039 ,  G11C7/22 ,  G11C8/10 ,  G11C2207/107

    Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

    Abstract translation: 存储器访问命令，列地址和多个写入数据值经由外部信令链路在集成电路存储器芯片内被接收。 响应于存储器访问命令，集成电路存储器芯片（i）解码列地址以从构成读出放大器组的多个读出放大器中选择地址指定的读出放大器，（ii）读取第一数据，构成 通过多个读取数据值，从地址指定的读出放大器中，和（iii）用地址指定的读出放大器中的第一数据用由一个或多个写数据值构成的第二数据和一个或多个 的读取数据值。

    Memory component that performs data write from pre-programmed register
    38.
    发明授权
    Memory component that performs data write from pre-programmed register 有权

    公开(公告)号：US11204863B2

    公开(公告)日：2021-12-21

    申请号：US16735303

    申请日：2020-01-06

    Applicant: Rambus Inc.

    Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

    IPC: G06F12/02 ,  G11C7/22 ,  G11C8/10 ,  G11C7/10

    Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

    SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE
    40.
    发明申请
    SINGLE COMMAND, MULTIPLE COLUMN-OPERATION MEMORY DEVICE 审中-公开

    公开(公告)号：US20200257619A1

    公开(公告)日：2020-08-13

    申请号：US16735303

    申请日：2020-01-06

    Applicant: Rambus Inc.

    Inventor： Thomas J. Sheffler ,  Lawrence Lai ,  Liang Peng ,  Bohuslav Rychlik

    IPC: G06F12/02 ,  G11C7/10 ,  G11C8/10 ,  G11C7/22

    Abstract: A memory access command, column address and plurality of write data values are received within an integrated-circuit memory chip via external signaling links. In response to the memory access command, the integrated-circuit memory chip (i) decodes the column address to select address-specified sense amplifiers from among a plurality of sense amplifiers that constitute a sense amplifier bank, (ii) reads first data, constituted by a plurality of read data values, out of the address-specified sense amplifiers, and (iii) overwrites the first data within the address-specified sense amplifiers with second data constituted by one or more of the write data values and by one or more of the read data values.

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