公开(公告)号：US20150207847A1

公开(公告)日：2015-07-23

申请号：US14600429

申请日：2015-01-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyung Kim ,  Young-Ky Kim ,  Jae-Duck Lee ,  Ki-Ho Cho ,  Ye-Sul HA

IPC: H04L29/08 ,  H04L29/06

Abstract: An apparatus and a method to support visible and audible communications using various multimedia services are provided. A method to provide communications using a multimedia service in a server of a communication system is provided. The method includes receiving a voice call connection request for a second device from a first device. The method also includes providing the first device with visual multimedia information generated in advance, over a web network in relation to the second device. The method further includes connecting a voice call between the first device and the second device.

Abstract translation: 提供了一种使用各种多媒体服务来支持可视和可听通信的装置和方法。 提供一种在通信系统的服务器中提供使用多媒体服务的通信的方法。 该方法包括从第一设备接收第二设备的语音呼叫连接请求。 该方法还包括向第一设备提供相对于第二设备通过web网络预先生成的视觉多媒体信息。 该方法还包括在第一设备和第二设备之间连接语音呼叫。

公开(公告)号：US20240251496A1

公开(公告)日：2024-07-25

申请号：US18628152

申请日：2024-04-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dohyung Kim ,  Seongchul Hong ,  Insung Kim ,  Jinhong Park ,  Jungchul Lee

IPC: H05G2/00 ,  G03F7/00 ,  H01L21/268

CPC classification number: H05G2/008 ,  H01L21/268 ,  G03F7/70033

Abstract: Disclosed are semiconductor manufacturing apparatuses and operating methods thereof. The semiconductor manufacturing apparatus includes an oscillation unit that includes a first seed laser, a second seed laser, and a seed module, wherein the first seed laser oscillates a first pulse, and wherein the second seed laser oscillates a second pulse, and an extreme ultraviolet generation unit configured to use the first and second pulses to generate extreme ultraviolet light. The seed module includes a plurality of mirrors configured to allow the first and second pulses to travel along first and second paths, respectively, and a pulse control optical system including a first optical element, a second optical element, and a third optical element. The pulse control optical system is on the second path that does not overlap the first path. The third optical element includes a lens between the first optical element and the second optical element.

公开(公告)号：US20240237362A9

公开(公告)日：2024-07-11

申请号：US18323440

申请日：2023-05-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIWON KIM ,  Dohyung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A three-dimensional semiconductor memory device may include a peripheral structure and a cell structure on the peripheral structure. The cell structure may include a substrate having first and second surfaces, which are opposite to each other, a stack including gate electrodes, which are stacked on the first surface of the substrate, an insulating layer on the second surface of the substrate, a penetration contact plug penetrating the first surface of the substrate, a first gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and spaced apart from the penetration contact plug, a second gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and connected to the penetration contact plug, a first gapfill spacer between the first gapfill conductive pattern and the substrate, and a second gapfill spacer between the second gapfill conductive pattern and the substrate.

公开(公告)号：US20240164101A1

公开(公告)日：2024-05-16

申请号：US18355450

申请日：2023-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Jiyoung Kim ,  Woosung Yang ,  Dohyung Kim ,  Sukkang Sung

IPC: H10B43/27 ,  H01L23/522 ,  H01L23/528 ,  H01L25/065 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00

CPC classification number: H10B43/27 ,  H01L23/5226 ,  H01L23/5283 ,  H01L25/0652 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B41/41 ,  H10B43/10 ,  H10B43/35 ,  H10B43/40 ,  H10B80/00 ,  H01L2225/06541

Abstract: Disclosed are 3D semiconductor memory devices and electronic systems including the same. The 3D semiconductor memory device comprises a first substrate, a peripheral circuit structure on the first substrate, and a cell array structure on the peripheral circuit structure. The cell array structure includes a second substrate, a stack structure between the second substrate and the peripheral circuit structure and including interlayer dielectric layers and conductive patterns that are stacked alternately with the interlayer dielectric layers, vertical channel structures that include respective portions the stack structure and include vertical semiconductor patterns, respectively, and connection vias that include respective portions the second substrate and are connected to respective top surfaces of the vertical semiconductor patterns.

公开(公告)号：US20240138157A1

公开(公告)日：2024-04-25

申请号：US18323440

申请日：2023-05-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： JIWON KIM ,  Dohyung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B80/00 ,  H01L23/00 ,  H01L25/00 ,  H01L25/065 ,  H01L25/18

CPC classification number: H10B80/00 ,  H01L24/08 ,  H01L24/80 ,  H01L25/0657 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/08145 ,  H01L2224/80895 ,  H01L2224/80896 ,  H01L2924/1431 ,  H01L2924/14511

Abstract: A three-dimensional semiconductor memory device may include a peripheral structure and a cell structure on the peripheral structure. The cell structure may include a substrate having first and second surfaces, which are opposite to each other, a stack including gate electrodes, which are stacked on the first surface of the substrate, an insulating layer on the second surface of the substrate, a penetration contact plug penetrating the first surface of the substrate, a first gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and spaced apart from the penetration contact plug, a second gapfill conductive pattern provided to penetrate the second surface of the substrate and the insulating layer and connected to the penetration contact plug, a first gapfill spacer between the first gapfill conductive pattern and the substrate, and a second gapfill spacer between the second gapfill conductive pattern and the substrate.

公开(公告)号：US20240105425A1

公开(公告)日：2024-03-28

申请号：US18244571

申请日：2023-09-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungwan Yoo ,  Jeongyeon Lee ,  Dohyung Kim ,  Jaehong Park ,  Dongchan Lim

IPC: H01J37/32 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01J37/32422 ,  H01J37/32522 ,  H01J37/32568 ,  H01J37/32715 ,  H01L21/02274 ,  H01L21/67098

Abstract: A substrate processing apparatus including a first chamber configured to accommodate a substrate therein and a second chamber including a heater provided in an internal space thereof, wherein the first chamber includes a target assembly configured to fix a target including a deposition material, a first ion gun configured to irradiate an ion beam onto the target to discharge deposition particles, which are ions of the deposition material, to the substrate, and a second ion gun configured to irradiate a hydrogen ion beam toward the substrate, the second ion gun includes a plasma generator configured to generate plasma, and a first grid electrode and a second grid electrode each configured to extract ions from the container, and the second chamber is configured to be provided with the substrate, on which the hydrogen ion beam has been irradiated, and perform thermal treatment on the substrate.

公开(公告)号：US20240049480A1

公开(公告)日：2024-02-08

申请号：US18120038

申请日：2023-03-10

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiyoung Kim ,  Dohyung Kim ,  Jiwon Kim ,  Sukkang Sung

IPC: H10B80/00 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B80/00 ,  H10B41/27 ,  H10B43/27

Abstract: A semiconductor device may include a first semiconductor structure including a lower substrate; and a second semiconductor structure on and bonded to the first semiconductor structure through a bonding structure. The second semiconductor structure may include: a pattern structure; an upper insulating layer on the pattern structure; a stack structure including gate electrode layers and interlayer insulating layers alternately stacked between the first semiconductor structure and the pattern structure; channel structures that extend through the stack structure; separation structures that extend through the stack structure and separate the stack structure. Each of the separation structures may include a first portion that extends through the stack structure and a second portion that extends from the first portion and extends through the pattern structure, and the second semiconductor structure further may include a spacer layer that separates the second portion of each separation structure from the pattern structure.

公开(公告)号：US20240008274A1

公开(公告)日：2024-01-04

申请号：US18178114

申请日：2023-03-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jiwon Kim ,  Dohyung Kim ,  Jiyoung Kim ,  Sukkang Sung

IPC: H10B43/27 ,  H01L29/423 ,  H01L23/528 ,  H10B43/40 ,  H10B43/35 ,  H10B41/35 ,  H10B41/27 ,  H10B41/40

CPC classification number: H10B43/27 ,  H01L29/42328 ,  H01L29/42344 ,  H01L23/5283 ,  H10B43/40 ,  H10B43/35 ,  H10B41/35 ,  H10B41/27 ,  H10B41/40

Abstract: An integrated circuit device includes a semiconductor substrate, and a common source structure on the substrate. A vertical stack of memory cell gate electrodes is provided, which extends between the common source structure and the substrate. The vertical stack of memory cell gate electrodes includes a first erase control gate electrode, and a plurality of word lines extending between the first erase control gate electrode and the substrate. At least one channel structure is provided, which vertically penetrates through the vertical stack of memory cell gate electrodes. A source protrusion pattern is provided, which is electrically connected to the common source structure. The source protrusion pattern extends sufficiently through the vertical stack of memory cell gate electrodes that a portion of the source protrusion pattern extends opposite a sidewall of the first erase control gate electrode.

公开(公告)号：US20230328968A1

公开(公告)日：2023-10-12

申请号：US18116537

申请日：2023-03-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Eunbin Seon ,  Jonghyun Kim ,  Hyunjung Lee ,  Dohyung Kim

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/482

Abstract: A semiconductor device includes a metal silicide layer on a substrate, and a contact plug structure on the metal silicide layer. The contact plug structure includes a metal pattern including a first metal, and a first barrier pattern covering a lower surface and a sidewall of the metal pattern and contacting the metal silicide layer. The first barrier pattern includes a second metal. The metal silicide layer includes silicon, the second metal, and a third metal different from the second metal.

公开(公告)号：US11785710B2

公开(公告)日：2023-10-10

申请号：US17947397

申请日：2022-09-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonseop Lee ,  Hwanwook Park ,  Jeonghoon Baek ,  Dohyung Kim ,  Seunghee Mun ,  Dongyoon Seo ,  Jinoh Ahn

IPC: G11C5/04 ,  H05K1/02 ,  H01L25/11 ,  H01L25/065 ,  G11C5/06 ,  G11C8/18 ,  G06F13/40

CPC classification number: H05K1/0246 ,  G06F13/4086 ,  G11C5/04 ,  G11C5/063 ,  G11C8/18 ,  H01L25/0657 ,  H01L25/112 ,  H05K1/025 ,  H05K2201/10159

Abstract: A module board and a memory module are provided. The module board includes a first branch line for connecting a clock signal terminal disposed on at least one surface to a first branch point; a first signal line for connecting the first branch point to a first module clock signal terminal; a second signal line for connecting the first module clock signal terminal to the kth module clock signal terminal and a first termination resistance terminal; a third signal line for connecting the first branch point to a (k+1)th module clock signal terminal; and a fourth signal line for connecting the (k+1)th module clock signal terminal to a 2kth module clock signal terminal and the second termination resistance terminal, wherein a length of the third signal line is greater than a sum of a length of the first signal line and a length of the second signal line.