公开(公告)号：US12034043B2

公开(公告)日：2024-07-09

申请号：US17479424

申请日：2021-09-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jinbum Kim ,  Gyeom Kim ,  Hyojin Kim ,  Haejun Yu ,  Seunghun Lee ,  Kyungin Choi

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/0665 ,  H01L29/0653 ,  H01L29/6656 ,  H01L29/78618 ,  H01L29/78696

Abstract: An integrated circuit device includes: a fin-type active region extending in a first horizontal direction on a substrate, a channel region on the fin-type active region, a gate line surrounding the channel region on the fin-type active region and extending in a second horizontal direction crossing the first horizontal direction, an insulating spacer covering a sidewall of the gate line, a source/drain region connected to the channel region on the fin-type active region and including a first portion facing the sidewall of the gate line with the insulating spacer therebetween, an air gap between the insulating spacer and the first portion of the source/drain region, and an insulating liner including a portion in contact with the source/drain region and a portion defining a size of the air gap.

公开(公告)号：US20240170552A1

公开(公告)日：2024-05-23

申请号：US18215254

申请日：2023-06-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyungbin Chun ,  Jinbum Kim ,  Gyeom Kim ,  Dahye Kim ,  Youngkwang Kim

IPC: H01L29/423 ,  H01L29/06 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L29/0673 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A semiconductor device including channels spaced apart from each other on a substrate; a gate structure extending on the substrate, the gate structure surrounding lower and upper surfaces and sidewalls of each of the channels; and a source/drain layer on the substrate, the source/drain layer contacting sidewalls of the channels and containing silicon-germanium, the source/drain layer including: a second epitaxial layer having a second germanium concentration; and a first epitaxial layer having a first germanium concentration smaller than the second germanium concentration, the first epitaxial layer covering a lower surface and sidewalls of the second epitaxial layer, wherein the first epitaxial layer includes a protruding portion that protrudes in the first direction and contacts the gate structure, and wherein the protruding portion has a facet that is not curved.

公开(公告)号：US20240014304A1

公开(公告)日：2024-01-11

申请号：US18170104

申请日：2023-02-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung Bin Chun ,  Jin Bum Kim ,  Dong Suk Shin ,  Gyeom Kim ,  Da Hye Kim

IPC: H01L29/775 ,  H01L29/66 ,  H01L29/423 ,  H01L29/08

CPC classification number: H01L29/775 ,  H01L29/66439 ,  H01L29/66742 ,  H01L29/42392 ,  H01L29/0847

Abstract: A semiconductor device includes a lower pattern on a substrate and protruding in a first direction, a source/drain pattern on the lower pattern and including a semiconductor liner film in contact with the lower pattern, and an epitaxial insulating liner extending along at least a portion of a sidewall of the semiconductor liner film, wherein the epitaxial insulating liner is in contact with the semiconductor liner film, wherein the semiconductor liner film includes a first portion, wherein the first portion of the semiconductor liner film includes a first point spaced apart from the lower pattern at a first height, and a second point spaced apart from the lower pattern at a second height, wherein the second height is greater than the first height, wherein a width of the semiconductor liner film in a second direction at the first point is less than a width of the semiconductor liner film in the second direction at the second point, and wherein the epitaxial insulating liner extends along at least a portion of a sidewall of the first portion of the semiconductor liner film.

公开(公告)号：US11869765B2

公开(公告)日：2024-01-09

申请号：US17853990

申请日：2022-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Dongwoo Kim ,  Jihye Yi ,  Jinbum Kim ,  Sangmoon Lee ,  Seunghun Lee

IPC: H01L21/02 ,  H01L21/285 ,  H01L21/768 ,  H01L21/8234 ,  H01L23/485 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/786 ,  H01L23/532 ,  B82Y10/00 ,  H01L29/10 ,  H01L29/161 ,  H01L21/28

CPC classification number: H01L21/02293 ,  H01L21/28518 ,  H01L21/76897 ,  H01L21/823431 ,  H01L21/823481 ,  H01L23/485 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/41791 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66439 ,  H01L29/66553 ,  H01L29/775 ,  H01L29/7848 ,  H01L29/78696

Abstract: A semiconductor device is provided. The semiconductor device includes: an active region on a semiconductor substrate; a channel region on the active region; a source/drain region adjacent to the channel region on the active region; a gate structure overlapping the channel region, on the channel region; a contact structure on the source/drain region; a gate spacer between the contact structure and the gate structure; and a contact spacer surrounding a side surface of the contact structure. The source/drain region includes a first epitaxial region having a recessed surface and a second epitaxial region on the recessed surface of the first epitaxial region, and the second epitaxial region includes an extended portion, extended from a portion overlapping the contact structure in a vertical direction, in a horizontal direction and overlapping the contact spacer in the vertical direction.

公开(公告)号：US20230420519A1

公开(公告)日：2023-12-28

申请号：US18110950

申请日：2023-02-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Da Hye Kim ,  Gyeom Kim ,  Jin Bum Kim ,  Su Jin Jung ,  Kyung Bin Chun

IPC: H01L29/08 ,  H01L29/06 ,  H01L29/161 ,  H01L29/423 ,  H01L29/775 ,  H01L21/02 ,  H01L29/66

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/161 ,  H01L29/42392 ,  H01L29/775 ,  H01L21/02532 ,  H01L29/66545 ,  H01L29/66439

Abstract: A semiconductor device having improved performance and reliability. The semiconductor device may include a lower pattern extending in a first direction, and a plurality of sheet patterns spaced apart from the lower pattern in a second direction perpendicular to the first direction. A plurality of gate structures may be on the lower pattern and spaced apart in the first direction, and a source/drain pattern, which may include a semiconductor liner film and a semiconductor filling film on the semiconductor liner film. A liner recess that is defined by an inner surface of the semiconductor liner film may include a plurality of width extension regions, and a width of each width extension region in the first direction may increase and then decreases, as a distance increases in the second direction from an upper surface of the lower pattern.

公开(公告)号：US20230317792A1

公开(公告)日：2023-10-05

申请号：US18073806

申请日：2022-12-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Gyeom Kim ,  Jinbum Kim ,  Sangmoon Lee ,  Dahye Kim ,  Kyungbin Chun

IPC: H01L29/423 ,  H01L29/775 ,  H01L29/06 ,  H01L29/167 ,  H01L29/08 ,  H01L29/417

CPC classification number: H01L29/0847 ,  H01L29/0673 ,  H01L29/167 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/775

Abstract: A semiconductor device includes an active region, a plurality of channel layers disposed to be spaced apart from each other in a vertical direction on the active region, a gate structure extending in a second direction to intersect the active region and the plurality of channel layers and surrounding the plurality of channel layers, a source/drain region disposed on the active region on at least one side of the gate structure and contacting the plurality of channel layers, and a contact plug connected to the source/drain region. The source/drain region includes a first epitaxial layer disposed on the active region and extending to contact the plurality of channel layers, second epitaxial layers disposed on the first epitaxial layer, each including impurities in a first concentration, and doping layers stacked alternately with the second epitaxial layers, each including the impurities in a second concentration higher than the first concentration.

公开(公告)号：US20210118877A1

公开(公告)日：2021-04-22

申请号：US16991530

申请日：2020-08-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaemun Kim ,  Gyeom Kim ,  Dahye Kim ,  Jinbum Kim ,  Kyungin Choi ,  llgyou Shin ,  Seunghun Lee

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/02

Abstract: An integrated circuit device includes: a fin-type active area protruding from a substrate, extending in a first direction parallel to an upper surface of the substrate, and including a first semiconductor material; an isolation layer arranged on the substrate and covering a lower portion of a sidewall of the fin-type active area, the isolation layer including an insulation liner conformally arranged on the lower portion of the sidewall of the fin-type active area, and an insulation filling layer on the insulation liner; a capping layer surrounding an upper surface and the sidewall of the fin-type active area, including a second semiconductor material different from the first semiconductor material, and with the capping layer having an upper surface, a sidewall, and a facet surface between the upper surface and the sidewall; and a gate structure arranged on the capping layer and extending in a second direction perpendicular to the first direction.

公开(公告)号：US20180355510A1

公开(公告)日：2018-12-13

申请号：US15869905

申请日：2018-01-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Keum Seok Park ,  Gyeom Kim ,  Yi Hwan Kim ,  Sun Jung Kim ,  Pan Kwi Park ,  Jeong Ho Yoo

IPC: C30B25/12 ,  C23C16/458

CPC classification number: C30B25/12 ,  C23C16/4585 ,  H01L29/0847 ,  H01L29/66795

Abstract: A semiconductor process chamber includes a susceptor, a base plate surrounding the susceptor, a liner on an inner sidewall of the base plate, and a preheat ring between the susceptor and the base plate and coplanar with the susceptor. The process chamber further includes an upper dome coupled to the base plate and covering an upper surface of the susceptor. The upper dome includes a first section on an upper surface of the base plate and a second section extending from the first section and overlapping the susceptor. The first section includes a first region on the upper surface of the base plate, a second region extending from the first region past the base plate, and a third region extending from the second region with a decreasing thickness to contact the second section.

公开(公告)号：US10141427B2

公开(公告)日：2018-11-27

申请号：US15187430

申请日：2016-06-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kyung-In Choi ,  Gyeom Kim ,  Hong-Sik Yoon ,  Bon-Young Koo ,  Wook-Je Kim

IPC: H01L29/66 ,  H01L29/768 ,  H01L29/78 ,  H01L21/8234 ,  H01L21/8238

Abstract: A semiconductor device includes a gate pattern on a substrate, a multi-channel active pattern under the gate pattern to cross the gate pattern and having a first region not overlapping the gate pattern and a second region overlapping the gate pattern, a diffusion layer in the multi-channel active pattern along the outer periphery of the first region and including an impurity having a concentration, and a liner on the multi-channel active pattern, the liner extending on lateral surfaces of the first region and not extending on a top surface of the first region. Related fabrication methods are also described.

公开(公告)号：US10008600B2

公开(公告)日：2018-06-26

申请号：US15685459

申请日：2017-08-24

Applicant: Samsung Electronics Co., Ltd.

Inventor： Nam Kyu Kim ,  Dong Chan Suh ,  Kwan Heum Lee ,  Byeong Chan Lee ,  Cho Eun Lee ,  Su Jin Jung ,  Gyeom Kim ,  Ji Eon Yoon

IPC: H01L29/08 ,  H01L29/78 ,  H01L29/165 ,  H01L29/417

CPC classification number: H01L29/7848 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/7834

Abstract: A semiconductor device may include: a semiconductor substrate, a device isolating layer embedded within the semiconductor substrate and defining an active region, a channel region formed in the active region, a gate electrode disposed above the channel region, a gate insulating layer provided between the channel region and the gate electrode, and a silicon germanium epitaxial layer adjacent to the channel region within the active region and including a first epitaxial layer containing a first concentration of germanium, a second epitaxial layer containing a second concentration of germanium, higher than the first concentration, and a third epitaxial layer containing a third concentration of germanium, lower than the second concentration, the first to third epitaxial layers being sequentially stacked on one another in that order.