公开(公告)号：US11296078B2

公开(公告)日：2022-04-05

申请号：US16431079

申请日：2019-06-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/423 ,  H01L29/10 ,  H01L29/06 ,  H01L21/28 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/306 ,  H01L21/762 ,  H01L29/66 ,  H01L21/3213 ,  H01L29/08 ,  H01L29/78 ,  H01L29/165

Abstract: A semiconductor device includes a plurality of semiconductor patterns that are sequentially stacked and spaced apart from each other on a substrate, and a gate electrode on the plurality of semiconductor patterns. The gate electrode includes a capping pattern and a work function pattern that are sequentially stacked on the plurality of semiconductor patterns. The capping pattern includes a first metal nitride layer including a first metal element, and a second metal nitride layer including a second metal element whose work function is greater than a work function of the first metal element. The first metal nitride layer is disposed between the second metal nitride layer and the plurality of semiconductor patterns. The first metal nitride layer is thinner than the second metal nitride layer.

公开(公告)号：US11217677B2

公开(公告)日：2022-01-04

申请号：US16584464

申请日：2019-09-26

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/49 ,  H01L27/088 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8234 ,  H01L29/423 ,  H01L29/66 ,  H01L21/3215 ,  H01L21/3115

Abstract: A semiconductor device includes a substrate having first and second active regions, first and second active patterns on the first and second active regions, first and second gate electrodes running across the first and second active patterns, and a high-k dielectric layer between the first active pattern and the first gate electrode and between the second active pattern and the second gate electrode. The first gate electrode includes a work function metal pattern and an electrode pattern. The second gate electrode includes a first work function metal pattern, a second work function metal pattern, and an electrode pattern. The first work function metal pattern contains the same impurity as that of the high-k dielectric layer. An impurity concentration of the first work function metal pattern of the second gate electrode is greater than that of the work function metal pattern of the first gate electrode.

公开(公告)号：US20200035801A1

公开(公告)日：2020-01-30

申请号：US16592309

申请日：2019-10-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Jae-Jung Kim ,  Jinkyu Jang ,  Sangyong Kim ,  Hoonjoo Na ,  Dongsoo Lee ,  Sangjin Hyun

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  B82Y10/00 ,  H01L29/775 ,  H01L27/11 ,  H01L29/786 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28

Abstract: A semiconductor device includes first semiconductor patterns vertically stacked on a substrate and vertically spaced apart from each other, and a first gate electrode on the first semiconductor patterns. The first gate electrode comprises a first work function metal pattern on a top surface, a bottom surface, and sidewalls of respective ones of the first semiconductor patterns, a barrier pattern on the first work function metal pattern, and a first electrode pattern on the barrier pattern. The first gate electrode has a first part between adjacent ones of the first semiconductor patterns. The barrier pattern comprises a silicon-containing metal nitride layer. The barrier pattern and the first electrode pattern are spaced apart from the first part.

公开(公告)号：US10468411B2

公开(公告)日：2019-11-05

申请号：US16017024

申请日：2018-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Wonkeun Chung ,  Gigwan Park ,  Huyong Lee ,  TaekSoo Jeon ,  Sangjin Hyun

IPC: H01L29/06 ,  H01L29/423 ,  H01L21/28 ,  H01L27/092 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66 ,  H01L29/43

Abstract: A semiconductor device includes a substrate having an active pattern thereon, a gate electrode intersecting the active pattern, and a spacer on a sidewall of the gate electrode. The gate electrode includes a first metal pattern adjacent to the active pattern. The first metal pattern has a first portion parallel to the sidewall and a second portion parallel to the substrate. A top surface of the first portion has a descent in a direction from the spacer towards the second portion.

公开(公告)号：US10217640B2

公开(公告)日：2019-02-26

申请号：US15797340

申请日：2017-10-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Soojung Choi ,  Moonkyun Song ,  Yoon Tae Hwang ,  Kyumin Lee ,  Sangjin Hyun

IPC: H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/311 ,  H01L21/324 ,  H01L27/092 ,  H01L29/51 ,  H01L21/3105

Abstract: A method of fabricating a semiconductor device includes forming first and second gate dielectric layers on first and second regions of a semiconductor substrate, respectively, forming a first metal-containing layer on the first and second gate dielectric layers, performing a first annealing process with respect to the first metal-containing layer, removing the first metal-containing layer from the first region, forming a second metal-containing layer on an entire surface of the semiconductor substrate, performing a second annealing process with respect to the second metal-containing layer, forming a gate electrode layer on the second metal-containing layer, and partially removing the gate electrode layer, the second metal-containing layer, the first metal-containing layer, the first gate dielectric layer, and the second gate dielectric layer to form first and second gate patterns on the first and second regions, respectively.

公开(公告)号：US08766366B2

公开(公告)日：2014-07-01

申请号：US13633663

申请日：2012-10-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo Na ,  Sangjin Hyun ,  Yugyun Shin ,  Hongbae Park ,  Sughun Hong ,  Hye-Lan Lee ,  Hyung-seok Hong

IPC: H01L29/49

CPC classification number: H01L21/823842 ,  H01L29/66545

Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.

Abstract translation: 制造半导体器件的方法包括在衬底上形成层间电介质，所述层间电介质包括分别设置在所述衬底中分开形成的第一和第二区域中的第一和第二开口; 形成填充所述第一和第二开口的第一导电层; 蚀刻第一导电层，使得第一开口的底表面露出，并且第二开口中的第一导电层的一部分保留; 以及形成填充所述第一开口和所述第二开口的一部分的第二导电层。

公开(公告)号：US12080712B2

公开(公告)日：2024-09-03

申请号：US17712272

申请日：2022-04-04

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghoon Lee ,  Jongho Park ,  Wandon Kim ,  Sangjin Hyun

IPC: H01L29/66 ,  H01L27/088 ,  H01L29/06 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L21/02 ,  H01L21/28 ,  H01L21/306 ,  H01L21/3213 ,  H01L21/762 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/165 ,  H01L29/78

CPC classification number: H01L27/0886 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/42392 ,  H01L29/4966 ,  H01L21/02532 ,  H01L21/28088 ,  H01L21/30604 ,  H01L21/32139 ,  H01L21/76224 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/82345 ,  H01L21/823468 ,  H01L21/823481 ,  H01L29/0847 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor device includes a plurality of semiconductor patterns that are sequentially stacked and spaced apart from each other on a substrate, and a gate electrode on the plurality of semiconductor patterns. The gate electrode includes a capping pattern and a work function pattern that are sequentially stacked on the plurality of semiconductor patterns. The capping pattern includes a first metal nitride layer including a first metal element, and a second metal nitride layer including a second metal element whose work function is greater than a work function of the first metal element. The first metal nitride layer is disposed between the second metal nitride layer and the plurality of semiconductor patterns. The first metal nitride layer is thinner than the second metal nitride layer.

公开(公告)号：US11728347B2

公开(公告)日：2023-08-15

申请号：US17494275

申请日：2021-10-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Weonhong Kim ,  Pilkyu Kang ,  Yuichiro Sasaki ,  Sungkeun Lim ,  Yongho Ha ,  Sangjin Hyun ,  Kughwan Kim ,  Seungha Oh

IPC: H01L27/12 ,  H01L21/762 ,  H01L27/02 ,  H01L29/78

CPC classification number: H01L27/1203 ,  H01L21/76224 ,  H01L27/0203 ,  H01L27/02 ,  H01L29/78

Abstract: An integrated circuit device includes an embedded insulation layer, a semiconductor layer on the embedded insulation layer, the semiconductor layer having a main surface, and a plurality of fin-type active areas protruding from the main surface to extend in a first horizontal direction and in parallel with one another, a separation insulation layer separating the semiconductor layer into at least two element regions adjacent to each other in a second horizontal direction intersecting the first horizontal direction, source/drain regions on the plurality of fin-type active areas, a first conductive plug on and electrically connected to the source/drain regions, a buried rail electrically connected to the first conductive plug while penetrating through the separation insulation layer and the semiconductor layer, and a power delivery structure arranged in the embedded insulation layer, the power delivery structure being in contact with and electrically connected to the buried rail.

公开(公告)号：US11676967B2

公开(公告)日：2023-06-13

申请号：US17749211

申请日：2022-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Guyoung Cho ,  Subin Shin ,  Donghyun Roh ,  Byung-Suk Jung ,  Sangjin Hyun

IPC: H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L27/0924 ,  H01L21/823821 ,  H01L29/0649 ,  H01L29/7851

Abstract: Disclosed is a semiconductor device comprising a substrate, a plurality of active patterns that protrude from the substrate, a device isolation layer between the active patterns, and a passivation layer that covers a top surface of the device isolation layer and exposes upper portions of the active patterns. The device isolation layer includes a plurality of first isolation parts adjacent to facing sidewalls of the active patterns, and a second isolation part between the first isolation parts. A top surface of the second isolation part is located at a lower level than that of top surfaces of the first isolation parts.

公开(公告)号：USRE49538E1

公开(公告)日：2023-05-30

申请号：US17070488

申请日：2020-10-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hoonjoo Na ,  Sangjin Hyun ,  Yugyun Shin ,  Hongbae Park ,  Sughun Hong ,  Hye-Lan Lee ,  Hyung-Seok Hong

IPC: H01L29/49 ,  H01L21/28 ,  H01L21/8234

CPC classification number: H01L21/28 ,  H01L29/49 ,  H01L21/8234

Abstract: A method of fabricating a semiconductor device includes forming an interlayer dielectric on a substrate, the interlayer dielectric including first and second openings respectively disposed in first and second regions formed separately in the substrate; forming a first conductive layer filling the first and second openings; etching the first conductive layer such that a bottom surface of the first opening is exposed and a portion of the first conductive layer in the second opening remains; and forming a second conductive layer filling the first opening and a portion of the second opening.