公开(公告)号：US09831172B2

公开(公告)日：2017-11-28

申请号：US14971402

申请日：2015-12-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Daeik Kim ,  Jemin Park ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L21/02 ,  H01L23/522 ,  H01L27/108

CPC classification number: H01L23/5223 ,  H01L23/5226 ,  H01L27/10814 ,  H01L27/10817 ,  H01L27/10855 ,  H01L27/10897 ,  H01L29/4236 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes a first device isolation region and a second device isolation region defining a first active region, a second active region, and a third active region in a substrate, a recess region exposing an upper surface of the first active region and upper surfaces of the first and second device isolation regions, and active buffer patterns on the second and third active regions. The first active region is located between the second and third active regions, the first device isolation region is located between the first and second active regions, the second device isolation region is located between the first and third active regions. Upper sidewalls of the second and third active regions are exposed in the recess region.

公开(公告)号：US09508649B2

公开(公告)日：2016-11-29

申请号：US14991020

申请日：2016-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Kyu Lee ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L29/78 ,  H01L29/423 ,  H01L23/528

CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first interconnection structure and a second interconnection structure which are disposed on a semiconductor substrate. A contact structure may be disposed between the first and second interconnection structures. A first lower air spacer may be disposed between the first interconnection structure and the contact structure. A second lower air spacer may be disposed between the second interconnection structure and the contact structure to be spaced apart from the first lower air spacer. An upper air spacer may be disposed on side surfaces of the contact structure to be connected to the first and second interconnection structures.

Abstract translation: 提供半导体器件。 半导体器件可以包括设置在半导体衬底上的第一互连结构和第二互连结构。 接触结构可以设置在第一和第二互连结构之间。 第一下部空气间隔件可以设置在第一互连结构和接触结构之间。 第二下部空气间隔件可以设置在第二互连结构和接触结构之间以与第一下部空气间隔件间隔开。 上空气隔离件可以设置在接触结构的侧表面上，以连接到第一和第二互连结构。

公开(公告)号：US20160211215A1

公开(公告)日：2016-07-21

申请号：US14991020

申请日：2016-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyeon-Kyu Lee ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L23/532 ,  H01L29/423 ,  H01L23/528 ,  H01L29/78

CPC classification number: H01L23/5329 ,  H01L21/7682 ,  H01L21/76895 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53295 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/4236 ,  H01L29/7827 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor devices are provided. The semiconductor devices may include a first interconnection structure and a second interconnection structure which are disposed on a semiconductor substrate. A contact structure may be disposed between the first and second interconnection structures. A first lower air spacer may be disposed between the first interconnection structure and the contact structure. A second lower air spacer may be disposed between the second interconnection structure and the contact structure to be spaced apart from the first lower air spacer. An upper air spacer may be disposed on side surfaces of the contact structure to be connected to the first and second interconnection structures.

Abstract translation: 提供半导体器件。 半导体器件可以包括设置在半导体衬底上的第一互连结构和第二互连结构。 接触结构可以设置在第一和第二互连结构之间。 第一下部空气间隔件可以设置在第一互连结构和接触结构之间。 第二下部空气间隔件可以设置在第二互连结构和接触结构之间以与第一下部空气间隔件间隔开。 上空气隔离件可以设置在接触结构的侧表面上，以连接到第一和第二互连结构。

公开(公告)号：US11929324B2

公开(公告)日：2024-03-12

申请号：US18133575

申请日：2023-04-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Keunnam Kim ,  Sohyun Park ,  Jin-Hwan Chun ,  Wooyoung Choi ,  Sunghee Han ,  Inkyoung Heo ,  Yoosang Hwang

IPC: H01L23/48 ,  G11C5/10 ,  H01L21/768 ,  H01L23/52 ,  H01L23/528 ,  H01L29/06 ,  H01L29/423 ,  H10B12/00

CPC classification number: H01L23/528 ,  G11C5/10 ,  H01L21/76831 ,  H01L29/0649 ,  H01L29/4236 ,  H10B12/485

Abstract: The semiconductor device provided comprises a substrate that includes active regions that extends in a first direction and a device isolation layer that defines the active regions, word lines that run across the active regions in a second direction that intersects the first direction, bit-line structures that intersect the active regions and the word lines and that extend in a third direction that is perpendicular to the second direction, first contacts between the bit-line structures and the active regions, spacer structures on sidewalls of the bit-line structures, and second contacts that are between adjacent bit-line structures and are connected to the active regions. Each of the spacer structures extends from the sidewalls of the bit-line structures onto a sidewall of the device isolation layer.

公开(公告)号：US11844212B2

公开(公告)日：2023-12-12

申请号：US17748261

申请日：2022-05-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok Lee ,  Junsoo Kim ,  Hui-Jung Kim ,  Bong-Soo Kim ,  Satoru Yamada ,  Kyupil Lee ,  Sunghee Han ,  HyeongSun Hong ,  Yoosang Hwang

IPC: H10B41/27 ,  H01L23/532 ,  G11C7/18 ,  G11C8/14 ,  H10B41/35 ,  G11C11/404 ,  G11C11/4097 ,  H01L49/02

CPC classification number: H10B41/27 ,  G11C7/18 ,  G11C8/14 ,  H01L23/53295 ,  H01L28/60 ,  H10B41/35 ,  G11C11/404 ,  G11C11/4097

Abstract: A semiconductor memory device includes a stack structure including a plurality of layers vertically stacked on a substrate. Each of the plurality of layers includes a first dielectric layer, a semiconductor layer, and a second dielectric layer that are sequentially stacked, and a first conductive line in the second dielectric layer and extending in a first direction. The device also includes a second conductive line extending vertically through the stack structure, and a capacitor in the stack structure and spaced apart from the second conductive line. The semiconductor layer includes semiconductor patterns extending in a second direction intersecting the first direction between the first conductive line and the substrate. The second conductive line is between a pair of the semiconductor patterns adjacent to each other in the first direction. An end of each of the semiconductor patterns is electrically connected to a first electrode of the capacitor.

公开(公告)号：US11805639B2

公开(公告)日：2023-10-31

申请号：US17372634

申请日：2021-07-12

Applicant: Samsung Electronics Co., Ltd.

Inventor： Euna Kim ,  Keunnam Kim ,  Kiseok Lee ,  Wooyoung Choi ,  Sunghee Han

IPC: H10B12/00 ,  H01L23/528

CPC classification number: H10B12/315 ,  H01L23/528 ,  H10B12/0335 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device includes a substrate including an active region, a first bitline structure and a second bitline structure that extend side by side on the substrate, a storage node contact electrically connected to the active region between the first and second bitline structures, a lower landing pad between the first and second bitline structures and on the storage node contact, an upper landing pad in contact with the first bitline structure and electrically connected to the lower landing pad, and a capping insulating layer. A lower surface of the upper landing pad in contact with the first bitline structure and a lower surface of the capping insulating layer in contact with the lower landing pad each include a portion in which a horizontal separation distance is increased from the adjacent upper landing pad in a direction toward the substrate.

公开(公告)号：US11728167B2

公开(公告)日：2023-08-15

申请号：US17680996

申请日：2022-02-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Dongjun Lee ,  Keunnam Kim ,  Daehyoun Kim ,  Taejin Park ,  Sunghee Han

IPC: H01L21/033 ,  H01L21/027 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L21/0337 ,  H01L21/0273 ,  H01L21/31144 ,  H01L21/76816

Abstract: A hardmask structure including a plurality of hardmask layers is formed on a target layer in a first area and a second area, a first photoresist pattern in the first area and a second photoresist pattern in the second area are formed, a reversible hardmask pattern including a plurality of openings is formed by transferring shapes of the first and second photoresist patterns to a reversible hardmask layer that is one of the plurality of hardmask layers, a gap-fill hardmask pattern is formed by filling some of the plurality of openings formed in the first area with a gap-fill hardmask pattern material, and a feature pattern is formed in the target layer by transferring a shape of the gap-fill hardmask pattern to the target layer in the first area and a shape of the reversible hardmask pattern to the target layer in the second area.

公开(公告)号：US11688779B2

公开(公告)日：2023-06-27

申请号：US17387427

申请日：2021-07-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hui-Jung Kim ,  Junhyeok Ahn ,  Jae Hyun Yoon ,  Myeong-Dong Lee ,  Seok Hwan Lee ,  Sunghee Han ,  Inkyoung Heo

IPC: H01L29/417 ,  H01L29/06 ,  H01L29/08 ,  H01L29/16 ,  H01L29/45 ,  H01L27/108

CPC classification number: H01L29/41775 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1606 ,  H01L27/10814 ,  H01L29/45

Abstract: A semiconductor memory device includes a substrate having a first active pattern including first and second source/drain regions, a gate electrode intersecting the first active pattern and disposed between the first and second source/drain regions, a bit line intersecting the first active pattern and electrically connected to the first source/drain region, a spacer disposed on a sidewall of the bit line, a contact electrically connected to the second source/drain region and spaced apart from the bit line with the spacer interposed therebetween, an interface layer disposed between the second source/drain region and the contact, and forming an ohmic contact between the second source/drain region and the contact, and a data storage element disposed on the contact. A bottom of the contact is lower than a top surface of the substrate. The contact is formed of a metal, a conductive metal nitride, and/or a combination thereof.

公开(公告)号：US11600570B2

公开(公告)日：2023-03-07

申请号：US17097337

申请日：2020-11-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyo-Sub Kim ,  Sohyun Park ,  Daewon Kim ,  Dongoh Kim ,  Eun A Kim ,  Chulkwon Park ,  Taejin Park ,  Kiseok Lee ,  Sunghee Han

IPC: H01L23/535 ,  H01L21/768 ,  H01L27/108 ,  H01L23/532

Abstract: A semiconductor memory device is disclosed. The device may include first and second impurity regions provided in a substrate and spaced apart from each other, the second impurity region having a top surface higher than the first impurity region, a device isolation pattern interposed between the first and second impurity regions, a first contact plug, which is in contact with the first impurity region and has a bottom surface lower than the top surface of the second impurity region, a gap-fill insulating pattern interposed between the first contact plug and the second impurity region, a first protection spacer interposed between the gap-fill insulating pattern and the second impurity region, and a first spacer, which is in contact with a side surface of the first contact plug and the device isolation pattern and is interposed between the first protection spacer and the gap-fill insulating pattern.

公开(公告)号：US20220344344A1

公开(公告)日：2022-10-27

申请号：US17720664

申请日：2022-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Taejin Park ,  Taehoon Kim ,  Kyujin Kim ,  Chulkwon Park ,  Sunghee Han ,  Yoosang Hwang

IPC: H01L27/108

Abstract: An integrated circuit device includes a substrate having an active region and a word line trench therein. The word line trench includes a lower portion having a first width, and an upper portion, which extends between the lower portion and a surface of the substrate and has a second width that is greater than the first width. A word line is provided, which extends in and adjacent a bottom of the word line trench. A gate insulation layer is provided, which extends between the word line and sidewalls of the lower portion of the word line trench. An electrically insulating gate capping layer is provided in the upper portion of the word line trench. An insulation liner is provided, which extends between the gate capping layer and sidewalls of the upper portion of the word line trench. The gate insulation layer extends between the insulation liner and a portion of the gate capping layer, which extends within the upper portion of the word line trench.