中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

45 records (took 0.057 seconds)

    TWO-SIDED ADJACENT MEMORY CELL INTERFERENCE MITIGATION
    37.
    发明申请
    TWO-SIDED ADJACENT MEMORY CELL INTERFERENCE MITIGATION 有权

    公开(公告)号：US20220180940A1

    公开(公告)日：2022-06-09

    申请号：US17114256

    申请日：2020-12-07

    Applicant: SanDisk Technologies LLC

    Inventor： Eran Sharon ,  Idan Alrod ,  Alexander Bazarsky

    IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08 ,  G11C16/10 ,  G11C16/34 ,  H01L25/065 ,  H01L23/00 ,  H01L27/11582

    Abstract: Technology for two-sided adjacent memory cell interference mitigation in a non-volatile storage system is disclosed. During reading of target memory cells, the storage system applies a suitable magnitude read pass voltage to a first unselected word line adjacent to a target word line to compensate for interference from adjacent cells on the first unselected word line while applying a suitable magnitude read reference voltage to the target word line to compensate for interference from adjacent cells on a second unselected word line on the other side of the target word line. The read pass voltage may compensate for interference due to charge being added to when programming cells on the first unselected word line after programming the target cells. The read reference voltage may compensate for interference due to charge movement near the target cells that results from charge stored in the cells on the second unselected word line.

    Command sequence for first read solution for memory
    39.
    发明授权
    Command sequence for first read solution for memory 有权

    公开(公告)号：US10262743B2

    公开(公告)日：2019-04-16

    申请号：US15440185

    申请日：2017-02-23

    Applicant: SanDisk Technologies LLC

    Inventor： Idan Alrod ,  Eran Sharon ,  Alon Eyal ,  Liang Pang ,  Evgeny Mekhanik

    IPC: G11C7/00 ,  G11C16/26 ,  G11C16/34 ,  G11C16/08 ,  G11C16/04

    Abstract: Techniques are provided for improving the accuracy of read operations of memory cells, where the threshold voltage of a memory cell can shift depending on when the read operation occurs. A command is issued for performing a conditioning operation which helps to transition the memory cells so that their threshold voltages are at predictable levels. In one approach, the conditioning operation is performed by applying a voltage pulse to one or more word lines in response to a trigger, such as detecting that a duration since a last sensing operation exceeds a threshold, detecting that a duration since a last performance of the conditioning operation exceeds a threshold, or a detecting that a read command has been issued. Moreover, the peak power consumption required to perform the conditioning operation can be reduced for various configurations of a memory device on one or more die.

    Non-volatile memory with corruption recovery
    40.
    发明授权
    Non-volatile memory with corruption recovery 有权

    公开(公告)号：US10198315B2

    公开(公告)日：2019-02-05

    申请号：US15056070

    申请日：2016-02-29

    Applicant: SANDISK TECHNOLOGIES LLC

    Inventor： Eran Sharon ,  Idan Alrod

    IPC: G06F11/10 ,  G11C29/04 ,  H03M13/09 ,  G11C29/52 ,  H03M13/29

    Abstract: A non-volatile storage system is provided that includes a mechanism to restore data that has been corrupted beyond the limits of traditional error correction. The system creates first level parity information for each subset of data to form multiple sets of programmable data, with each set of programmable data including a subset of data and corresponding first level parity. Separate second level parity is created for each set of programmable data. The system creates combined second level parity information based on a function of separate second level parity information for the multiple sets of programmable data. If a set of programmable data is found to be corrupt, the corrupt subset of data is recovered using the corrupt subset of data read from the non-volatile storage system, the corresponding first level parity read from the non-volatile storage system and the combined second level parity information.

Patent Agency Ranking