公开(公告)号：US20250149406A1

公开(公告)日：2025-05-08

申请号：US19019260

申请日：2025-01-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Youngsun KO ,  Seungwon IM ,  Jerome TEYSSEYRE ,  Michael J. SEDDON

IPC: H01L23/44 ,  H01L21/48 ,  H05K7/20

Abstract: Implementations of a semiconductor package may include one or more semiconductor die directly coupled to only a direct leadframe attach (DLA) leadframe including two or more leads; and a coating covering the one or more semiconductor die and the DLA leadframe where when the semiconductor package is coupled into an immersion cooling enclosure, the coating may be in contact with a dielectric coolant while the two or more leads extend out of the immersion cooling enclosure.

公开(公告)号：US20240413148A1

公开(公告)日：2024-12-12

申请号：US18808298

申请日：2024-08-19

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Tiburcio A. MALDO ,  Keunhyuk LEE ,  Jerome TEYSSEYRE

IPC: H01L27/06 ,  H01L21/48 ,  H01L23/13 ,  H01L23/498

Abstract: Described implementations provide wireless, surface mounting of at least two semiconductor devices on opposed surfaces of a leadframe, to provide an isolated, three-dimensional (3D) configuration. The described implementations minimize electrical failures, even for very high voltage applications, while enabling low inductance and high current. Resulting semiconductor device packages have mounting surfaces that provide desired levels of isolation and insulation, while still enabling straightforward mounting techniques, such as soldering, as well as high levels of thermal reliability.

公开(公告)号：US20240258268A1

公开(公告)日：2024-08-01

申请号：US18632548

申请日：2024-04-11

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Inpil YOO ,  Maria Cristina ESTACIO ,  Jerome TEYSSEYRE ,  Seungwon IM ,  JooYang EOM

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31 ,  H01L23/495 ,  H01L23/52

CPC classification number: H01L24/92 ,  H01L21/56 ,  H01L23/49527 ,  H01L23/49575 ,  H01L23/52 ,  H01L24/24 ,  H01L24/29 ,  H01L24/32 ,  H01L24/40 ,  H01L24/73 ,  H01L24/82 ,  H01L24/83 ,  H01L24/84 ,  H01L23/3107 ,  H01L23/49513 ,  H01L2224/24011 ,  H01L2224/24101 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24246 ,  H01L2224/29139 ,  H01L2224/32245 ,  H01L2224/40101 ,  H01L2224/40137 ,  H01L2224/73213 ,  H01L2224/73217 ,  H01L2224/73263 ,  H01L2224/73267 ,  H01L2224/82101 ,  H01L2224/8384 ,  H01L2224/8484 ,  H01L2224/92142 ,  H01L2224/92144

Abstract: Implementations of a semiconductor package may include two or more die, each of the two more die coupled to a metal layer at a drain of each of the two more die, the two or more die and each metal layer arranged in two parallel planes; a first interconnect layer coupled at a source of each of the two more die; a second interconnect layer coupled to a gate of each of the two or more die and to a gate package contact through one or more vias; and an encapsulant that encapsulates the two or more die and at least a portion of the first interconnect layer, each metal layer, and the second interconnect layer.

公开(公告)号：US20240222231A1

公开(公告)日：2024-07-04

申请号：US18608662

申请日：2024-03-18

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Yusheng LIN ,  Jerome TEYSSEYRE ,  Huibin CHEN

IPC: H01L23/492 ,  H01L21/48 ,  H01L23/00 ,  H01L23/14 ,  H01L23/373 ,  H01L23/498 ,  H01L23/50 ,  H01L23/538 ,  H01L25/18

CPC classification number: H01L23/492 ,  H01L21/4853 ,  H01L21/4875 ,  H01L23/14 ,  H01L23/49811 ,  H01L23/50 ,  H01L24/06 ,  H01L24/14 ,  H01L23/3735 ,  H01L23/5383 ,  H01L25/18

Abstract: A semiconductor die includes an electronic device formed in the semiconductor die. The semiconductor die further includes a plurality of device contact pads disposed on a surface of the semiconductor die. The plurality of device contact pads are electrically connected to the electronic device. The plurality of device contact pads include at least an emitter contact pad and a signal sense contact pad, and a dummy device contact pad disposed on the surface of the semiconductor die. The dummy device contact pad provides an area for a solder joint between the semiconductor die and a substrate in addition to an area provided by the plurality of device contact pads.

公开(公告)号：US20240128197A1

公开(公告)日：2024-04-18

申请号：US18487835

申请日：2023-10-16

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Olaf ZSCHIESCHANG ,  Oseob JEON ,  Jihwan KIM ,  Roveendra PAUL ,  Klaus NEUMAIER ,  Jerome TEYSSEYRE

IPC: H01L23/538 ,  H01L21/56 ,  H01L23/00

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L24/24 ,  H01L24/82 ,  H01L25/072

Abstract: In a general aspect, an assembly includes a panel of organic substrate core material having a cavity defined therein, a module substrate disposed in the cavity, and a semiconductor die disposed on the module substrate. The assembly also includes a layer of prepreg organic substrate material, and a metal layer. The module substrate and the semiconductor die are embedded in the cavity by the layer of prepreg organic substrate material and the metal layer. The metal layer is electrically coupled with at least one of the semiconductor die or the module substrate.

公开(公告)号：US20240128140A1

公开(公告)日：2024-04-18

申请号：US18485966

申请日：2023-10-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Seungwon IM ,  Jeonghyuk PARK ,  Keunhyuk LEE ,  Jerome TEYSSEYRE ,  Paolo BILARDO

IPC: H01L23/31 ,  H01L21/56 ,  H01L23/367 ,  H01L23/495

CPC classification number: H01L23/3121 ,  H01L21/56 ,  H01L23/367 ,  H01L23/49555

Abstract: In one general aspect, an apparatus can include a semiconductor die, a molding material disposed around at least a portion of the semiconductor die, and a pair of leads electrically coupled to the semiconductor die and aligned along a first direction from the molding material. The molding material can define an elongated protrusion aligned along a second direction orthogonal to the first direction, and a notch disposed between the pair of leads.

公开(公告)号：US20230225044A1

公开(公告)日：2023-07-13

申请号：US18154303

申请日：2023-01-13

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Oseob JEON ,  Seungwon IM ,  Roveendra PAUL ,  Jerome TEYSSEYRE

IPC: H05K1/02 ,  H05K1/18 ,  H03K17/687

CPC classification number: H05K1/0216 ,  H05K1/181 ,  H03K17/6871 ,  H05K2201/10166 ,  H03K2217/0063 ,  H03K2217/0072

Abstract: In general aspect, a module can include a substrate having a semiconductor circuit implemented thereon, and a negative power supply terminal electrically coupled with the semiconductor circuit via the substrate. The negative power supply terminal includes a connection tab arranged in a first plane. The module also includes a first positive power supply terminal electrically and a second positive power supply terminal that are coupled with the semiconductor circuit via the substrate. The first positive power supply terminal being laterally disposed from the negative power supply terminal, and including a connection tab arranged in the first plane. The second positive power supply terminal is laterally disposed from the negative power supply terminal and arranged in the first plane, such that the negative power supply terminal is disposed between the first positive power supply terminal and the second positive power supply terminal.

公开(公告)号：US20230207411A1

公开(公告)日：2023-06-29

申请号：US18172641

申请日：2023-02-22

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Maria Cristina ESTACIO ,  Jerome TEYSSEYRE ,  Elsie Agdon CABAHUG

IPC: H01L23/31 ,  H01L29/16 ,  H01L23/00 ,  H01L21/56 ,  H01L23/367 ,  H01L23/495

CPC classification number: H01L23/3107 ,  H01L29/1608 ,  H01L24/09 ,  H01L21/565 ,  H01L23/367 ,  H01L23/49524 ,  H01L23/49582 ,  H01L2224/02379

Abstract: A semiconductor package is disclosed. Specific implementations of a semiconductor package may include: one or more semiconductor die coupled between a baseframe and a clip, the baseframe including a gate pad of the baseframe coupled with a gate pad of the one or more semiconductor die, and a source pad of the baseframe coupled with a source pad of the one or more semiconductor die, where the gate pad of the baseframe extends beyond a perimeter of the one or more semiconductor die.

公开(公告)号：US20230075519A1

公开(公告)日：2023-03-09

申请号：US18055139

申请日：2022-11-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Maria Cristina ESTACIO ,  Seungwon IM

IPC: H01L23/495 ,  H01L23/00 ,  H01L29/16 ,  H01L23/473 ,  H01L23/433 ,  H01L23/373 ,  H01L23/31 ,  H01L21/56

Abstract: In a general aspect, an apparatus can include an inner package including a first silicon carbide die having a die gate conductor coupled to a common gate conductor, and a second silicon carbide die having a die gate conductor coupled to the common gate conductor. The apparatus can include an outer package including a substrate coupled to the common gate conductor, and a clip coupled to the inner package and coupled to the substrate.

公开(公告)号：US20220406767A1

公开(公告)日：2022-12-22

申请号：US17822844

申请日：2022-08-29

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Jerome TEYSSEYRE ,  Inpil YOO ,  JooYang EOM

IPC: H01L25/00 ,  H01L25/18 ,  H01L23/367 ,  H01L23/467 ,  H01L23/473 ,  H01L25/07

Abstract: According to an aspect, a power module package includes a plurality of power modules including a first power module and a second power module, a plurality of heat sinks including a first heat sink coupled to the first power module and a second heat sink coupled to the second power module, and a module carrier coupled to the plurality of power modules, where the module carrier includes a first region defining a first heat-sink slot and a second region defining a second heat-sink slot. The first heat sink extends at least partially through the first heat-sink slot and the second heat sink extends at least partially through the second heat-sink slot. The power module package includes a housing coupled to the module carrier and a ring member located between the module carrier and the housing.