公开(公告)号：US20170084696A1

公开(公告)日：2017-03-23

申请号：US15259941

申请日：2016-09-08

申请人： Changhyun Lee ,  Heonkyu Lee ,  Shinhwan Kang ,  Youngwoo Park

发明人： Changhyun Lee ,  Heonkyu Lee ,  Shinhwan Kang ,  Youngwoo Park

IPC分类号： H01L29/10 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565

摘要： A three-dimensional semiconductor memory device includes a stack on a substrate including electrodes vertically stacked on a substrate, lower insulating patterns disposed between the stack and the substrate, the lower insulating patterns being adjacent to both sidewalls of the stack and being spaced apart from each other, a plurality of vertical structures penetrating the stack and being connected to the substrate, and a data storing pattern between the stack and the vertical structures, the data storing pattern including a portion disposed between the lowermost one of the electrodes and the substrate.

公开(公告)号：US09595333B2

公开(公告)日：2017-03-14

申请号：US14702895

申请日：2015-05-04

申请人： Jaesung Sim ,  Youngwoo Park

发明人： Jaesung Sim ,  Youngwoo Park

IPC分类号： G11C11/34 ,  G11C16/10 ,  G11C11/56 ,  G11C16/24 ,  G11C16/04

CPC分类号： G11C16/10 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/24

摘要： According to example embodiments, a nonvolatile memory device includes a plurality of cell strings on a horizontal semiconductor layer. Each of the cell strings including a plurality of memory cells stacked in a direction perpendicular to the horizontal semiconductor layer. According to example embodiments, a programming method of the nonvolatile memory device includes setting up bitlines corresponding the cell strings, setting up a plurality of string select lines connected to the cell strings, and applying a negative voltage lower to a ground select line. The ground select line is connected to a plurality of ground select transistors between the memory cells and the semiconductor layer. The string select lines extend in a direction intersecting the bitlines. The negative voltage is lower than a ground voltage.

摘要翻译： 根据示例性实施例，非易失性存储器件包括在水平半导体层上的多个单元串。 每个单元串包括在与水平半导体层垂直的方向上堆叠的多个存储单元。 根据示例实施例，非易失性存储器件的编程方法包括设置与单元串对应的位线，设置连接到单元串的多个串选择线，以及向接地选择线施加较低的负电压。 接地选择线连接到存储器单元和半导体层之间的多个接地选择晶体管。 字符串选择行在与位线相交的方向上延伸。 负电压低于接地电压。

公开(公告)号：US20160163733A1

公开(公告)日：2016-06-09

申请号：US15009040

申请日：2016-01-28

申请人： Jintaek Park ,  Youngwoo Park

发明人： Jintaek Park ,  Youngwoo Park

IPC分类号： H01L27/115

CPC分类号： H01L27/11582 ,  G11C5/02 ,  G11C5/063 ,  H01L27/249 ,  H01L45/10 ,  H01L45/1226 ,  H01L45/146 ,  H01L45/148

摘要： A three-dimensional semiconductor device includes bit lines provided on a substrate, a gate structure provided between the substrate and the bit lines, a common source line provided between the gate structure and the bit lines, and channel pipes connecting the bit lines to the common source line. Each of the channel pipes may include a pair of vertical portions extending through the gate structure and a horizontal portion connecting the vertical portions. The pair of vertical portions are provided under a pair of the bit lines arranged adjacent to each other, respectively.

摘要翻译： 三维半导体器件包括设置在衬底上的位线，设置在衬底和位线之间的栅极结构，设置在栅极结构和位线之间的公共源极线，以及将位线连接到公共端 源线。 每个通道管可以包括延伸穿过栅极结构的一对垂直部分和连接垂直部分的水平部分。 一对垂直部分分别设置在彼此相邻布置的一对位线下方。

公开(公告)号：US09362226B2

公开(公告)日：2016-06-07

申请号：US14637755

申请日：2015-03-04

申请人： Jaegoo Lee ,  Youngwoo Park

发明人： Jaegoo Lee ,  Youngwoo Park

IPC分类号： H01L29/06 ,  H01L29/40 ,  H01L23/02 ,  H01L23/528 ,  H01L23/522 ,  H01L27/115

CPC分类号： H01L27/11582 ,  H01L23/5226 ,  H01L23/528 ,  H01L27/11548 ,  H01L27/11556 ,  H01L27/11575 ,  H01L2924/0002 ,  H01L2924/00

摘要： A three-dimensional (3D) semiconductor device includes a stack of conductive layers spaced from each other in a vertical direction, the stack having a staircase-shaped section in a connection region, and ends of the conductive layers constituting treads of the staircase-shaped section, respectively. The 3D semiconductor device further includes buffer patterns disposed on and protruding above the respective ends of the conductive layers, an interconnection structure disposed above the stack and including conductive lines, and contact plugs extending vertically between the conductive lines and the buffer patterns and electrically connected to the conductive layers of the stack via the buffer patterns.

摘要翻译： 三维（3D）半导体器件包括在垂直方向上彼此间隔开的导电层的堆叠，所述堆叠在连接区域中具有阶梯状部分，并且导电层的端部构成阶梯状的胎面 部分。 所述3D半导体器件还包括设置在所述导电层的各个端部之上并突出于所述导电层的各个端部上方的缓冲图案，布置在所述堆叠之上并且包括导电线的互连结构以及在所述导电线与所述缓冲图案之间垂直延伸的电连接 经由缓冲器图案的堆叠的导电层。

公开(公告)号：US09299707B2

公开(公告)日：2016-03-29

申请号：US14150452

申请日：2014-01-08

申请人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

发明人： Jaeduk Lee ,  Youngwoo Park ,  Jintaek Park ,  Dohyun Lee ,  Kohji Kanamori

IPC分类号： H01L27/108 ,  H01L27/105 ,  H01L27/115 ,  G11C16/10 ,  G11C16/14

CPC分类号： H01L27/1052 ,  G11C16/10 ,  G11C16/14 ,  H01L27/11524 ,  H01L27/11556

摘要： Provided are three-dimensional semiconductor devices and methods of operating the same. The three-dimensional semiconductor devices may include active patterns arranged on a substrate to have a multi-layered and multi-column structure and drain patterns connected to respective columns of the active patterns. The methods may include a layer-selection step connecting a selected one of layers of the active patterns selectively to the drain patterns. For example, the layer-selection step may be performed in such a way that widths of depletion regions to be formed in end-portions of the active patterns are differently controlled depending on to a height from the substrate.

摘要翻译： 提供三维半导体器件及其操作方法。 三维半导体器件可以包括布置在衬底上的有源图案，以具有连接到有源图案的相应列的多层和多列结构以及漏极图案。 所述方法可以包括选择性地将有源图案的层中所选择的一个层连接到漏极图案的层选择步骤。 例如，层选择步骤可以以这样的方式执行，使得在有源图案的端部中形成的耗尽区的宽度根据与基板的高度不同地被控制。

公开(公告)号：US20150303209A1

公开(公告)日：2015-10-22

申请号：US14656115

申请日：2015-03-12

申请人： Jintaek PARK ,  Yoocheol Shin ,  Youngwoo Park

发明人： Jintaek PARK ,  Yoocheol Shin ,  Youngwoo Park

IPC分类号： H01L27/115 ,  H01L27/112

CPC分类号： H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11582

摘要： Semiconductor devices and methods of forming the semiconductor devices are provided. The semiconductor devices may include a peripheral circuit part that is disposed under a cell array circuit part. The peripheral circuit part may drive the cell array circuit part. The semiconductor devices may also include first conductive lines, which are connected to the peripheral circuit part, and second conductive lines, which are connected to the cell array circuit part. The first conductive lines and the second conductive lines may have substantially the same shape, and the first conductive lines may overlap with the second conductive lines in a connection region, respectively.

摘要翻译： 提供了形成半导体器件的半导体器件和方法。 半导体器件可以包括设置在单元阵列电路部分下的外围电路部分。 外围电路部分可以驱动单元阵列电路部分。 半导体器件还可以包括连接到外围电路部分的第一导线和连接到电池阵列电路部分的第二导线。 第一导线和第二导线可以具有基本上相同的形状，并且第一导线可以分别与连接区域中的第二导线重叠。

公开(公告)号：US20150294980A1

公开(公告)日：2015-10-15

申请号：US14681505

申请日：2015-04-08

申请人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

发明人： Jaegoo Lee ,  Youngwoo Park ,  Jaeduk Lee

IPC分类号： H01L27/115 ,  H01L29/66 ,  H01L21/285 ,  H01L21/28 ,  H01L21/768 ,  H01L29/792 ,  H01L29/423

CPC分类号： H01L27/11582 ,  H01L21/28282 ,  H01L21/28518 ,  H01L21/76877 ,  H01L29/66833 ,  H01L29/7926

摘要： Semiconductor devices are provided including an active pillar protruding from a substrate; a first gate electrode and a second gate electrode adjacent to a sidewall of the active pillar and vertically overlapping with each other, the first and second gate electrodes being insulated from each other; a first intergate insulating layer covering a first surface of the first gate electrode; and a second intergate insulating layer covering a second surface, opposite the first surface, of the second gate electrode and spaced apart from the first intergate insulating layer. The first intergate insulating layer and the second intergate insulating layer define an air gap therebetween.

摘要翻译： 提供半导体器件，其包括从基板突出的有源柱; 与所述有源柱的侧壁相邻并且彼此垂直重叠的第一栅电极和第二栅电极，所述第一栅电极和所述第二栅电极彼此绝缘; 覆盖所述第一栅电极的第一表面的第一隔间绝缘层; 以及覆盖所述第二栅电极的与所述第一表面相对的第二表面并与所述第一栅极绝缘层间隔开的第二栅极绝缘层。 第一隔间绝缘层和第二隔间绝缘层在其间形成气隙。

公开(公告)号：US08742488B2

公开(公告)日：2014-06-03

申请号：US13366818

申请日：2012-02-06

申请人： Jaegoo Lee ,  Kil-Su Jeong ,  Hansoo Kim ,  Youngwoo Park

发明人： Jaegoo Lee ,  Kil-Su Jeong ,  Hansoo Kim ,  Youngwoo Park

IPC分类号： H01L23/52

CPC分类号： H01L23/52 ,  H01L27/1157 ,  H01L27/11578 ,  H01L27/11582 ,  H01L2924/0002 ,  H01L2924/00

摘要： Example embodiments relate to a three-dimensional semiconductor memory device including an electrode structure on a substrate, the electrode structure including at least one conductive pattern on a lower electrode, and a semiconductor pattern extending through the electrode structure to the substrate. A vertical insulating layer may be between the semiconductor pattern and the electrode structure, and a lower insulating layer may be between the lower electrode and the substrate. The lower insulating layer may be between a bottom surface of the vertical insulating layer and a top surface of the substrate. Example embodiments related to methods for fabricating the foregoing three-dimensional semiconductor memory device.

摘要翻译： 示例实施例涉及一种三维半导体存储器件，其包括在衬底上的电极结构，该电极结构包括在下电极上的至少一个导电图案，以及半导体图案，其延伸穿过该电极结构到该衬底。 垂直绝缘层可以在半导体图案和电极结构之间，下绝缘层可以位于下电极和衬底之间。 下绝缘层可以在垂直绝缘层的底表面和基板的顶表面之间。 与制造上述三维半导体存储器件的方法相关的示例实施例。

公开(公告)号：US08735860B2

公开(公告)日：2014-05-27

申请号：US13742598

申请日：2013-01-16

申请人： Jintaek Park ,  Youngwoo Park ,  Jungdal Choi

发明人： Jintaek Park ,  Youngwoo Park ,  Jungdal Choi

IPC分类号： H01L29/02

CPC分类号： H01L45/1206 ,  H01L27/2436 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146 ,  H01L45/147 ,  H01L45/148 ,  H01L45/1683

摘要： A variable resistance memory device includes a selection transistor, which includes a first doped region and a second doped region, a vertical electrode coupled to the first doped region of the selection transistor, a bit line coupled to the second doped region of the selection transistor, a plurality of word lines stacked on the substrate along a sidewall of the vertical electrode, variable resistance patterns between the word lines and the vertical electrode, and an insulating isolation layer between the word lines. The variable resistance patterns are spaced apart from each other in a direction normal to a top surface of the substrate by the insulating isolation layer.

摘要翻译： 可变电阻存储器件包括选择晶体管，其包括第一掺杂区和第二掺杂区，耦合到选择晶体管的第一掺杂区的垂直电极，耦合到选择晶体管的第二掺杂区的位线， 沿着垂直电极的侧壁堆叠在基板上的多个字线，字线和垂直电极之间的可变电阻图案以及字线之间的绝缘隔离层。 可变电阻图案通过绝缘隔离层在垂直于衬底的顶表面的方向上彼此间隔开。

公开(公告)号：US20130140623A1

公开(公告)日：2013-06-06

申请号：US13757273

申请日：2013-02-01

申请人： Changhyun LEE ,  ByoungKeun Son ,  Youngwoo Park

发明人： Changhyun LEE ,  ByoungKeun Son ,  Youngwoo Park

IPC分类号： H01L29/792

CPC分类号： H01L29/788 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L29/04 ,  H01L29/7889 ,  H01L29/792 ,  H01L29/7926

摘要： A three-dimensional semiconductor memory device may include gap-fill insulating layers extending upward from a substrate, an electrode structure delimited by sidewalls of the gap-fill insulating layers, vertical structures provided between adjacent ones of the gap-fill insulating layers to penetrate the electrode structure, and at least one separation pattern extending along the gap-fill insulating layers and penetrating at least a portion of the electrode structure. The separation pattern may include at least one separation semiconductor layer.

摘要翻译： 三维半导体存储器件可以包括从衬底向上延伸的间隙填充绝缘层，由间隙填充绝缘层的侧壁限定的电极结构，设置在相邻的间隙填充绝缘层之间的垂直结构以穿透 电极结构，以及沿间隙填充绝缘层延伸并穿透电极结构的至少一部分的至少一个分离图案。 分离图案可以包括至少一个分离半导体层。