公开(公告)号：US20180053732A1

公开(公告)日：2018-02-22

申请号：US15667315

申请日：2017-08-02

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Ho BAEK ,  Moon Hee YI ,  Kyung Sang LIM

IPC: H01L23/552 ,  H01L23/00 ,  H01L23/538 ,  H01L23/13

CPC classification number: H01L23/552 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49811 ,  H01L23/5386 ,  H01L23/5389 ,  H01L24/20 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/1035 ,  H01L2225/107 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/18162 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/00012

Abstract: A fan-out semiconductor package includes a semiconductor chip disposed in a through-hole of a first connection member having the through-hole and a second connection member disposed on an active surface of the semiconductor chip. A plurality of dummy vias surrounding the semiconductor chip are disposed in the first connection member.

公开(公告)号：US20160105967A1

公开(公告)日：2016-04-14

申请号：US14815868

申请日：2015-07-31

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD

Inventor： Jae Hoon CHOI ,  Jung Hyun PARK ,  Yong Ho BAEK ,  Hea Sung KIM ,  Jung Hyun CHO ,  Il Jong SEO

IPC: H05K1/18 ,  H05K1/02 ,  H05K3/40 ,  H05K3/30 ,  H05K3/46 ,  H05K3/18 ,  H05K1/11 ,  H05K3/00

CPC classification number: H05K1/183 ,  H01L2224/04105 ,  H01L2224/2518 ,  H05K1/185 ,  H05K3/0097 ,  H05K3/305 ,  H05K3/306 ,  H05K3/4682 ,  H05K3/4697 ,  H05K2201/10015 ,  H05K2201/10636 ,  H05K2203/1536 ,  Y02P70/611

Abstract: An embedded board includes an insulating layer and an electronic device embedded in the insulating layer. A first circuit pattern is embedded to contact a bottom surface of the insulating layer, and a second circuit pattern protrudes from the bottom surface of the insulating layer. A via is bonded to the device and the second circuit pattern.

Abstract translation: 嵌入式板包括绝缘层和嵌入绝缘层中的电子器件。 嵌入第一电路图形以接触绝缘层的底表面，并且第二电路图案从绝缘层的底表面突出。 通孔连接到器件和第二电路图案。

公开(公告)号：US20160044788A1

公开(公告)日：2016-02-11

申请号：US14794632

申请日：2015-07-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jung Hyun PARK ,  Yong Ho BAEK ,  Jae Hoon CHOI

IPC: H05K1/18 ,  H05K3/42 ,  H05K3/46 ,  H05K3/30 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K1/185 ,  H05K3/4682 ,  H05K2201/0195 ,  H05K2203/1469

Abstract: There is provided a printed circuit board including: a first insulating layer; a first circuit pattern formed on a first surface of the first insulating layer; an adhesive layer provided on a second surface of the first insulating layer; and an electronic component disposed on the adhesive layer and enclosed by the first insulating layer and a second insulating layer formed on the first insulating layer.

Abstract translation: 提供一种印刷电路板，包括：第一绝缘层; 形成在所述第一绝缘层的第一表面上的第一电路图案; 设置在所述第一绝缘层的第二表面上的粘合剂层; 以及设置在所述粘合剂层上并被所述第一绝缘层包围的电子部件和形成在所述第一绝缘层上的第二绝缘层。

公开(公告)号：US20150342054A1

公开(公告)日：2015-11-26

申请号：US14667001

申请日：2015-03-24

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Ho BAEK ,  Hyo Seung NAM ,  Jae Ean LEE ,  Ju Yeon BONG ,  Jung Hyun CHO ,  Kyung Hwan KO

IPC: H05K1/18 ,  H05K3/10 ,  H05K3/32 ,  H05K3/46 ,  H05K1/02 ,  H05K1/11

CPC classification number: H05K3/10 ,  H05K1/182 ,  H05K3/284 ,  H05K3/32 ,  H05K3/4682 ,  H05K2201/096 ,  H05K2201/10015 ,  Y10T29/49156

Abstract: Embodiments of the invention provide an embedded coreless substrate, and a method for manufacturing the same. According to an embodiment of the present invention, an embedded coreless substrate includes an insulating layer, a conductive pattern including a plurality of circuit pattern layers formed in(on) the insulating layer and a plurality of vias for vertically connecting the circuit pattern layers, and at least one embedded device, which is partially embedded in the insulating layer and an outer circuit pattern layer among the plurality of circuit pattern layers and of which an electrode in an embedded portion is partially or entirely covered with the outer circuit pattern layer to fix the embedded portion, is provided. Further, a method for manufacturing an embedded coreless substrate is provided.

Abstract translation: 本发明的实施例提供一种嵌入式无芯基板及其制造方法。 根据本发明的实施例，嵌入式无芯基板包括绝缘层，包括形成在绝缘层中的多个电路图案层的导电图案和用于垂直连接电路图案层的多个通孔，以及 部分嵌入绝缘层中的至少一个嵌入式装置和多个电路图案层之中的外部电路图案层，并且其中嵌入部分中的电极部分或全部被外部电路图案层覆盖以将 嵌入式部分。 此外，提供了一种用于制造嵌入式无芯基板的方法。

公开(公告)号：US20150251278A1

公开(公告)日：2015-09-10

申请号：US14448150

申请日：2014-07-31

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Jae Ean LEE ,  Jung Hyun CHO ,  Kyung Hwan KO ,  Yong Ho BAEK

IPC: B23K35/02 ,  H05K1/18 ,  B23K35/24

CPC classification number: B23K35/0244 ,  B23K35/0222 ,  B23K35/0238 ,  B23K35/24 ,  B23K35/26 ,  B23K35/262 ,  B32B15/01 ,  C22C12/00 ,  C22C28/00 ,  C22C43/00 ,  H05K3/3463 ,  H05K3/3478 ,  H05K2203/041 ,  Y10T428/12493 ,  Y10T428/12681

Abstract: A solder ball has a core, an intermediate layer, and a surface layer. In one aspect, the intermediate layer melts at a temperature higher than that of the surface layer. In another aspect, the core is made of a material that maintains a liquid state through a temperature range of from about 20° C. to about 110° C., the intermediate layer is made of a material that maintains a solid state at temperatures up to about 270° C., and the surface layer is made of a material with a melting temperature of about 230° C. to about 270° C. In another aspect, the first metal and the second metal are materials that do not form an intermetallic compound with another material in the solder ball. The solder ball may be used in a circuit board.

Abstract translation: 焊球具有芯，中间层和表面层。 在一个方面，中间层在高于表面层的温度下熔化。 在另一方面，芯由保持液态在约20℃至约110℃的温度范围内的材料制成，中间层由在高温下保持固态的材料制成 至约270℃，表面层由熔点为约230℃至约270℃的材料制成。在另一方面，第一金属和第二金属是不形成 金属间化合物与焊球中的另一种材料。 焊球可用于电路板。

公开(公告)号：US20190229060A1

公开(公告)日：2019-07-25

申请号：US16375302

申请日：2019-04-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Ho BAEK ,  Sang Kun KIM ,  Ye Jeong KIM ,  Jae Ean LEE ,  Jae Hoon CHOI

IPC: H01L23/538 ,  H01L21/66 ,  H01L21/48 ,  H05K1/18 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: An electronic component package includes first and second wiring parts including insulating layers, conductive patterns formed in the insulating layers, and conductive vias penetrating through the insulating layers, to be connected to the conductive patterns, respectively; a frame disposed between the first and second wiring parts and having conductive connection parts electrically connecting one or more through-holes with the first and second wiring parts and an electronic component disposed to be surrounded by the through-hole, to thereby be connected to the first wiring part, wherein the conductive patterns formed to be adjacent to the electronic component among the conductive patterns of the first wiring part are embedded in the insulating layer of the first wiring part.

公开(公告)号：US20190189583A1

公开(公告)日：2019-06-20

申请号：US16015815

申请日：2018-06-22

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Ho BAEK ,  Young Sik HUR ,  Joo Hwan JUNG

IPC: H01L23/00 ,  H01L23/498

Abstract: A semiconductor package includes a core member having a cavity penetrating through first and second surfaces, a semiconductor chip disposed in the cavity and having an active surface having connection, a passive component module disposed in the cavity, including a plurality of passive components and a resin portion encapsulating the plurality of passive components, and having a mounting surface from which connection terminals of the passive components are exposed, a connection member on the second surface and including a redistribution layer connected to the connection pads of the semiconductor chip and connection terminals of some of the plurality of passive components, connection terminals of the others of the plurality of passive components not being connected to the redistribution layer.

公开(公告)号：US20190173195A1

公开(公告)日：2019-06-06

申请号：US15972905

申请日：2018-05-07

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Doo Il KIM ,  Jung Hyun CHO ,  Won Wook SO ,  Young Sik HUR ,  Yong Ho BAEK

IPC: H01Q21/00 ,  H01Q1/38 ,  H01Q1/02 ,  H01Q1/24

Abstract: An antenna module includes a connection member including at least one wiring layer and at least one insulating layer; an integrated circuit (IC) package disposed on a first surface of the connection member; and an antenna package including a plurality of antenna members and a plurality of feed vias, and disposed on a second surface of the connection member, wherein the IC package includes: an IC having an active surface electrically connected to at least one wiring layer and an inactive surface opposing the active surface, and generating the RF signal; a heat sink member disposed on the inactive surface of the IC; and an encapsulant encapsulating at least portions of the IC and the heat sink member.

公开(公告)号：US20190013300A1

公开(公告)日：2019-01-10

申请号：US15882440

申请日：2018-01-29

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Ho BAEK ,  Joo Hwan JUNG ,  Young Sik HUR ,  Jung Chul GONG ,  Han KIM

IPC: H01L25/16 ,  H01L23/498 ,  H01L23/31 ,  H01L23/552 ,  H01L49/02

Abstract: A fan-out semiconductor package module includes: a core member having a first through hole and a second through hole; a semiconductor chip disposed in the first through hole, and having an active surface and an inactive surface opposite the active surface, the active surface having a connection pad disposed thereon; at least one first passive component disposed in the second through hole; a first encapsulant encapsulating the core member encapsulating at least a portion of each of the core member and the at least one first passive component; a second encapsulant encapsulating at least a portion of the inactive surface of the semiconductor chip; and a connection member disposed on the core member, the active surface of the semiconductor chip, and the at least one first passive component, and including a redistribution layer electrically connected to the connection pad and the at least one first passive component.

公开(公告)号：US20190013282A1

公开(公告)日：2019-01-10

申请号：US15807075

申请日：2017-11-08

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Moon Hee YI ,  Yong Ho BAEK ,  Tae Seong KIM

IPC: H01L23/00

Abstract: A fan-out semiconductor package includes: a support member having a through-hole; a semiconductor chip disposed in the through-hole and having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least portions of the support member and the semiconductor chip; and a connection member disposed on the support member and the active surface of the semiconductor chip and including a redistribution layer electrically connected to the connection pads. The support member includes a glass plate and an insulating layer connected to the glass plate.