公开(公告)号：US09209179B2

公开(公告)日：2015-12-08

申请号：US14253439

申请日：2014-04-15

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jin-Wook Lee ,  Kang-Ill Seo

IPC: H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L29/0692 ,  H01L29/66795 ,  H01L29/7855 ,  H01L29/7856

Abstract: A semiconductor device is provided. A substrate includes first and second active fins disposed in a row along a first direction. The first and second active fins are spaced apart from each other. A first dummy gate and a second dummy gate are disposed on the substrate and are extended in a second direction intersecting the first direction. The first dummy gate covers an end portion of the first active fin. The second dummy gate covers an end portion of the second active fin facing the end portion of the first active fin. A first dummy spacer is disposed on a sidewall of the first dummy gate. A second dummy spacer is disposed on a sidewall of the second dummy gate. The sidewall of the second dummy gate faces the sidewall of the first dummy gate. The first dummy spacer is in contact with the second dummy spacer.

Abstract translation: 提供半导体器件。 衬底包括沿着第一方向排成一排的第一和第二活性鳍。 第一和第二活动翅片彼此间隔开。 第一伪栅极和第二伪栅极设置在基板上并沿与第一方向相交的第二方向延伸。 第一伪栅极覆盖第一有源鳍片的端部。 第二伪栅极覆盖面向第一有源鳍片的端部的第二有源鳍片的端部。 第一虚拟间隔物设置在第一伪栅极的侧壁上。 第二虚拟间隔物设置在第二虚拟栅极的侧壁上。 第二伪栅极的侧壁面向第一虚拟栅极的侧壁。 第一假间隔件与第二假间隔件接触。

公开(公告)号：US12274092B2

公开(公告)日：2025-04-08

申请号：US18406345

申请日：2024-01-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Myunggil Kang ,  Kang-Ill Seo

IPC: H10D86/00 ,  G01R27/02 ,  H01L21/66 ,  H01L23/535 ,  H10D30/67 ,  H10D84/01 ,  H10D84/03 ,  H10D84/85 ,  H10D88/00

Abstract: Resistance measuring structures for a stacked integrated circuit device are provided. The resistance measuring structures may include a first Complementary Field Effect Transistor (CFET) stack, a second CFET stack, and a conductive connection. The first CFET may include a first upper transistor that includes a first upper drain region and a first lower transistor that is between the substrate and the first upper transistor and includes a first lower drain region. The second CFET may include a second upper transistor that includes a second upper drain region and a second lower transistor that is between the substrate and the second upper transistor and includes a second lower drain region. The conductive connection may electrically connect the first upper drain region and the second upper drain region.

公开(公告)号：US20250105153A1

公开(公告)日：2025-03-27

申请号：US18752851

申请日：2024-06-25

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jintae Kim ,  Panjae Park ,  Kang-Ill Seo

IPC: H01L23/528 ,  H01L23/48 ,  H01L27/092

Abstract: Integrated circuit devices are provided. An integrated circuit device includes a substrate and a cell that has a plurality of transistors. The transistors include an upper transistor having an upper channel region. Moreover, the transistors include a lower transistor between the substrate and the upper transistor. The lower transistor includes a lower channel region. The integrated circuit device includes a power line extending longitudinally in a first horizontal direction below the substrate and defining a cell boundary of the cell that extends longitudinally in the first horizontal direction. The integrated circuit device includes a cell boundary signal metal pattern on the cell and extending longitudinally in the first horizontal direction over the cell boundary and connected to at least two transistors of the plurality of transistors. Related methods of forming integrated circuit devices are also provided.

公开(公告)号：US12087669B1

公开(公告)日：2024-09-10

申请号：US18543111

申请日：2023-12-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jaehong Lee ,  Sooyoung Park ,  Wonhyuk Hong ,  Kang-Ill Seo

IPC: H01L21/00 ,  H01L21/8238 ,  H01L23/48 ,  H01L27/07 ,  H01L27/092 ,  H01L29/06 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/775 ,  H01L29/786

CPC classification number: H01L23/481 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823842 ,  H01L21/823871 ,  H01L27/0727 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/41733 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/775 ,  H01L29/78696

Abstract: Integrated circuit devices and methods of forming the same. As an example, an integrated circuit device may include a substrate; a first transistor structure on the substrate; a second transistor structure stacked in a vertical direction on the first transistor structure; an isolation layer between the first transistor structure and the second transistor structure in the vertical direction; and a diode structure on the substrate and adjacent to the first transistor structure in a horizontal direction. The diode structure may be part of a discharging path between a gate electrode of the second transistor structure and the substrate. The discharging path may extend through the isolation layer.

公开(公告)号：US20240096984A1

公开(公告)日：2024-03-21

申请号：US18160341

申请日：2023-01-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongjin Lee ,  Tae Sun Kim ,  Wonhyuk Hong ,  Seungchan Yun ,  Kang-Ill Seo

IPC: H01L29/417 ,  H01L23/528 ,  H01L29/06 ,  H01L29/40 ,  H01L29/423 ,  H01L29/775

CPC classification number: H01L29/41766 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/775

Abstract: Integrated circuit devices and methods of forming the same are provided. The methods may include providing a substrate structure including a substrate, a bottom insulator and a semiconductor region between the substrate and the bottom insulator, the semiconductor region extending in a first direction; forming first and second preliminary transistor structures on the bottom insulator, wherein and the bottom insulator may include first and second portions that the first and second preliminary transistor structures respectively overlap, and a third portion between the first and second portions; replacing the third portion of the bottom insulator with a bottom semiconductor layer; forming a source/drain region between the first and second preliminary transistor structures; replacing the substrate and the semiconductor region with a backside insulator; forming a power contact in the backside insulator, wherein the source/drain region may overlap the power contact; and forming a power rail.

公开(公告)号：US11843001B2

公开(公告)日：2023-12-12

申请号：US17380999

申请日：2021-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Byounghak Hong ,  Seunghyun Song ,  Ki-Il Kim ,  Gunho Jo ,  Kang-Ill Seo

IPC: H04L45/745 ,  H04L12/46 ,  H04L45/52 ,  H01L27/12 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/822 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/8221 ,  H01L21/823412 ,  H01L21/823456 ,  H01L21/84 ,  H01L27/088

Abstract: Nanosheet transistor devices are provided. A nanosheet transistor device includes a transistor stack that includes a lower nanosheet transistor having a first nanosheet width and a lower gate width. The transistor stack also includes an upper nanosheet transistor that is on the lower nanosheet transistor and that has a second nanosheet width and an upper gate width that are different from the first nanosheet width and the lower gate width, respectively. Related methods of forming a nanosheet transistor device are also provided.

公开(公告)号：US11177260B2

公开(公告)日：2021-11-16

申请号：US16805550

申请日：2020-02-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dong-Il Bae ,  Kang-Ill Seo

IPC: H01L27/092 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L27/088 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/3105 ,  H01L29/775

Abstract: A semiconductor device includes a first fin structure disposed on a substrate. The first fin structure extends in a first direction. A first sacrificial layer pattern is disposed on the first fin structure. The first sacrificial layer pattern includes a left portion and a right portion arranged in the first direction. A dielectric layer pattern is disposed on the first fin structure and interposed between the left and right portions of the first sacrificial layer pattern. A first active layer pattern extending in the first direction is disposed on the first sacrificial layer pattern and the dielectric layer pattern. A first gate electrode structure is disposed on a portion of the first active layer pattern. The portion of the first active layer is disposed on the dielectric layer pattern. The first gate electrode structure extends in a second direction crossing the first direction.

公开(公告)号：US20200020685A1

公开(公告)日：2020-01-16

申请号：US16275761

申请日：2019-02-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Mingyu KIM ,  Kang-Ill Seo

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78 ,  H01L21/308 ,  H01L21/8234

Abstract: A semiconductor device including a semiconductor substrate having a recessed top portion and a non-recessed top portion, a first fin protruding upward from a non-recessed top portion with a first thickness, a second fin protruding upward from the recessed top portion with a second thickness greater than the first thickness, a first gate structure on the non-recessed top portion and surrounding the first fin to a first height from the non-recessed top portion, and a second gate structure on the recessed top portion and surrounding the second fin to a second height different from the first height from the recessed top portion may be provided.

公开(公告)号：US10128254B2

公开(公告)日：2018-11-13

申请号：US15187529

申请日：2016-06-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dae-Jin Kwon ,  Kang-Ill Seo

IPC: H01L29/423 ,  H01L27/11 ,  H01L23/528 ,  H01L29/78

Abstract: A semiconductor device includes a substrate, a first pattern, a first gate electrode, and a second pattern. The first pattern is disposed on the substrate and extends in a first direction substantially vertical to an upper surface of the substrate, and includes a first part, a second part and a third part sequentially disposed on the substrate. The first gate electrode is connected to the second part and extends in a second direction different from the first direction. The second pattern is disposed on the substrate, extends in the first direction, is connected to the first part, and does not contact the first gate electrode.

公开(公告)号：US10038077B2

公开(公告)日：2018-07-31

申请号：US15234484

申请日：2016-08-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong-Hyuk Kim ,  Kang-Ill Seo ,  Hyun-Jae Kang ,  Deok-Han Bae

IPC: H01L21/00 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/033 ,  H01L21/311 ,  H01L21/308

CPC classification number: H01L29/66795 ,  H01L21/0337 ,  H01L21/3086 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823821 ,  H01L27/0924

Abstract: A method of fabricating a semiconductor device is provided. A plurality of target patterns is formed on a substrate. The plurality of target patterns is extended in parallel to each other along a first direction. A first mask pattern extending in the first direction and including a plurality of first openings is formed. A second mask pattern extending in a second direction crossing the first direction and including a plurality of second openings is formed. Each second opening overlaps each first opening to form an overlapped opening region. A region of the plurality of target patterns is etched through the overlapped opening region using the first mask pattern and the second mask pattern as a etch mask. The region of the plurality of target patterns is overlapped with the overlapped opening region.