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    STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET
    31.
    发明申请
    STRAINED STACKED NANOSHEET FETS AND/OR QUANTUM WELL STACKED NANOSHEET 审中-公开
    应变堆叠的纳米晶体管和/或量子堆积的纳米硅片

    公开(公告)号：US20160111284A1

    公开(公告)日：2016-04-21

    申请号：US14918954

    申请日：2015-10-21

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jorge A. Kittl ,  Borna J. Obradovic ,  Robert C. Bowen ,  Mark S. Rodder

    IPC: H01L21/02 ,  H01L29/06 ,  H01L29/10 ,  H01L21/283 ,  H01L21/306

    CPC classification number: H01L29/0669 ,  H01L21/0245 ,  H01L21/02463 ,  H01L21/02466 ,  H01L21/02505 ,  H01L21/02532 ,  H01L21/02546 ,  H01L21/02549 ,  H01L29/0665 ,  H01L29/1054 ,  H01L29/7781 ,  H01L29/7782 ,  H01L29/7783

    Abstract: Exemplary embodiments provide for fabricating a nanosheet stack structure having one or more sub-stacks. Aspects of the exemplary embodiments include: growing an epitaxial crystalline initial stack of one or more sub-stacks, each of the sub-stacks having at least three layers, a sacrificial layer A, and at least two different non-sacrificial layers B and C having different material properties, wherein the non-sacrificial layers B and C layers are kept below a thermodynamic or kinetic critical thickness corresponding to metastability during all processing, and wherein the sacrificial layer An is placed only at a top or a bottom of each of the sub-stacks, and each of the sub-stacks is connected to an adjacent sub-stack at the top or the bottom using one of the sacrificial layers A; proceeding with fabrication flow of nanosheet devices, such that pillar structures are formed at each end of the epitaxial crystalline stack that to hold the nanosheets in place after selective etch of the sacrificial layers; and selectively removing sacrificial layers A to all non-sacrificial layers B and C, while the remaining layers in the stack are held in place by the pillar structures so that after removal of the sacrificial layers An, each of the sub-stacks contains the non-sacrificial layers B and C.

    Abstract translation: 示例性实施例提供制造具有一个或多个子堆叠的纳米片堆叠结构。 示例性实施例的方面包括：生长一个或多个子堆叠的外延晶体初始堆叠，每个子堆叠具有至少三个层，牺牲层A和至少两个不同的非牺牲层B和C 具有不同的材料性质，其中非牺牲层B和C层保持低于在所有加工期间对应于亚稳态的热力学或动力学临界厚度，并且其中牺牲层An仅被放置在每个的顶部或底部 并且每个子堆叠使用牺牲层A之一连接到顶部或底部的相邻子堆叠; 继续纳米片装置的制造流程，使得在外延晶体堆叠的每个端部处形成柱结构，以在选择性蚀刻牺牲层之后将纳米片保持在适当位置; 并且将牺牲层A选择性地去除所有非牺牲层B和C，而堆叠中的其余层被柱结构保持就位，使得在去除牺牲层An之后，每个子堆包含非牺牲层 - 层B和C.

    CRYSTALLINE MULTIPLE-NANOSHEET III-V CHANNEL FETS
    32.
    发明申请
    CRYSTALLINE MULTIPLE-NANOSHEET III-V CHANNEL FETS 有权
    晶体多层纳米III-V通道FET

    公开(公告)号：US20150123215A1

    公开(公告)日：2015-05-07

    申请号：US14270690

    申请日：2014-05-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Borna J. Obradovic ,  Jorge A. Kittl ,  Mark S. Rodder

    IPC: H01L29/10 ,  H01L29/78 ,  H01L29/51 ,  H01L29/20 ,  H01L29/49

    CPC classification number: H01L29/42392 ,  H01L29/78681 ,  H01L29/78696

    Abstract: A field effect transistor includes a body layer comprising a crystalline semiconductor channel region therein, and a gate stack on the channel region. The gate stack includes a crystalline semiconductor gate layer, and a crystalline semiconductor gate dielectric layer between the gate layer and the channel region. Related devices and fabrication methods are also discussed.

    Abstract translation: 场效应晶体管包括其中包括晶体半导体沟道区的主体层，以及沟道区上的栅叠层。 栅极堆叠包括晶体半导体栅极层和栅极层和沟道区之间的晶体半导体栅极介电层。 还讨论了相关设备和制造方法。

    METHODS OF FORMING A SEMICONDUCTOR LAYER INCLUDING GERMANIUM WITH LOW DEFECTIVITY
    33.
    发明申请
    METHODS OF FORMING A SEMICONDUCTOR LAYER INCLUDING GERMANIUM WITH LOW DEFECTIVITY 有权
    形成具有低缺陷度的锗的半导体层的方法

    公开(公告)号：US20150118829A1

    公开(公告)日：2015-04-30

    申请号：US14480869

    申请日：2014-09-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jorge A. Kittl ,  Mark S. Rodder

    IPC: H01L21/02

    CPC classification number: H01L21/02664 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02532

    Abstract: Methods of forming a semiconductor layer including germanium with low defectivity are provided. The methods may include sequentially forming a silicate glass layer, a diffusion barrier layer including nitride and an interfacial layer including oxide on a substrate. The methods may also include forming a first semiconductor layer on the interfacial layer and converting a portion of the first semiconductor layer into a second semiconductor layer having a germanium concentration therein that is higher than a germanium concentration of the first semiconductor layer.

    Abstract translation: 提供了形成具有低缺陷度的锗的半导体层的方法。 所述方法可以包括依次形成硅酸盐玻璃层，包含氮化物的扩散阻挡层和在衬底上包含氧化物的界面层。 所述方法还可以包括在界面层上形成第一半导体层，并将第一半导体层的一部分转换成其锗浓度高于第一半导体层的锗浓度的第二半导体层。

    Method of enabling sparse neural networks on memresistive accelerators
    35.
    发明授权
    Method of enabling sparse neural networks on memresistive accelerators 有权

    公开(公告)号：US11816563B2

    公开(公告)日：2023-11-14

    申请号：US16409487

    申请日：2019-05-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Titash Rakshit ,  Ryan M. Hatcher ,  Jorge A. Kittl ,  Borna J. Obradovic ,  Engin Ipek

    IPC: G06F11/07 ,  G06F11/10 ,  G06N3/08 ,  G06F17/16

    CPC classification number: G06N3/08 ,  G06F17/16

    Abstract: A method of storing a sparse weight matrix for a trained artificial neural network in a circuit including a series of clusters. The method includes partitioning the sparse weight matrix into at least one first sub-block and at least one second sub-block. The first sub-block includes only zero-value weights and the second sub-block includes non-zero value weights. The method also includes assigning the non-zero value weights in the at least one second sub-block to at least one cluster of the series of clusters of the circuit. The circuit is configured to perform matrix-vector-multiplication (MVM) between the non-zero value weights of the at least one second sub-block and an input vector during an inference process utilizing the artificial neural network. The sub-blocks containing all zero elements are power gated, thereby reducing overall energy consumption for inference.

    Interconnects having long grains and methods of manufacturing the same
    38.
    发明授权
    Interconnects having long grains and methods of manufacturing the same 有权

    公开(公告)号：US11289419B2

    公开(公告)日：2022-03-29

    申请号：US16942392

    申请日：2020-07-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Harsono Simka

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

    Abstract: A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.

    Interconnects having long grains and methods of manufacturing the same
    40.
    发明授权
    Interconnects having long grains and methods of manufacturing the same 有权

    公开(公告)号：US10763207B2

    公开(公告)日：2020-09-01

    申请号：US15939211

    申请日：2018-03-28

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jorge A. Kittl ,  Ganesh Hegde ,  Harsono Simka

    IPC: H01L23/522 ,  H01L21/768 ,  H01L23/528 ,  H01L23/532

    Abstract: A method of manufacturing metallic interconnects for an integrated circuit includes forming an interconnect layout including at least one line including a non-diffusing material, forming a diffusing barrier layer on the line, forming an opening extending completely through the diffusing barrier layer and exposing a portion of the line, depositing a diffusing layer on the diffusing barrier layer such that a portion of the diffusing layer contacts the portion of the line, and thermally reacting the diffusing layer to form the metallic interconnects. Thermally reacting the diffusing layer chemically diffuses a material of the diffusing layer into the at least one line and causes at least one crystalline grain to grow along a length of the at least one line from at least one nucleation site defined at an interface between the portions of the diffusing layer and the line.

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