公开(公告)号：US20180374869A1

公开(公告)日：2018-12-27

申请号：US15993756

申请日：2018-05-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kwang-soo KIM ,  Yong-seok KIM ,  Tae-hun KIM ,  Min-kyung BAE ,  Jae-hoon JANG ,  Kohji KANAMORI

IPC: H01L27/11582 ,  H01L29/78 ,  H01L29/08

CPC classification number: H01L27/11582 ,  H01L27/11565 ,  H01L29/0847 ,  H01L29/7827

Abstract: A semiconductor device includes a plurality of channel structures on a substrate, each channel structure extending in a first direction perpendicular to the substrate, and having a gate insulating layer and a channel layer, a common source extension region including a first semiconductor layer having an n-type conductivity between the substrate and the channel structures, a plurality of gate electrodes on the common source extension region and spaced apart from each other on a sidewall of each of the channel structures in the first direction, and a common source region on the substrate in contact with the common source extension region and including a second semiconductor layer having an n-type conductivity, wherein the gate insulating layer of each of the channel structures extends to cover an upper surface and at least a portion of a bottom surface of the common source extension region.

公开(公告)号：US20140063914A1

公开(公告)日：2014-03-06

申请号：US14015869

申请日：2013-08-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI

IPC: G11C13/00

CPC classification number: G11C13/0064 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/0097 ,  G11C2213/71 ,  G11C2213/77

Abstract: An erase verifying method includes applying a first voltage to a plurality of word lines connected to a memory cell block, and applying a second voltage less than the first voltage to a plurality of bit lines connected to the memory cell block. The method includes sensing bit line currents flowing through the plurality of bit lines, and comparing the sensed bit line currents with a reference current. The method also includes determining that the memory cell block has been sufficiently erased by a first erase operation if each of the sensed bit line currents is less than the reference current.

Abstract translation: 擦除验证方法包括：将第一电压施加到连接到存储单元块的多个字线，以及将小于第一电压的第二电压施加到连接到存储器单元块的多个位线。 该方法包括检测流过多个位线的位线电流，并将感测到的位线电流与参考电流进行比较。 该方法还包括如果每个感测到的位线电流小于参考电流，则通过第一擦除操作来确定存储器单元块已被充分擦除。

公开(公告)号：US20240224521A1

公开(公告)日：2024-07-04

申请号：US18428264

申请日：2024-01-31

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

CPC classification number: H10B43/27 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/35

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US20220415909A1

公开(公告)日：2022-12-29

申请号：US17903315

申请日：2022-09-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Haemin LEE ,  Jongwon KIM ,  Shinhwan KANG ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/1157 ,  H01L27/11578 ,  H01L27/11521 ,  H01L27/11556

Abstract: A semiconductor device includes a first stack group having first interlayer insulating layers and first gate layers, alternately and repeatedly stacked on a substrate and a second stack group comprising second interlayer insulating layers and second gate layers, alternately and repeatedly stacked on the first stack group. Separation structures pass through the first and second stack groups and include a first separation region and a second separation region. A vertical structure passes through the first and second stack groups and includes a first vertical region and a second vertical region. A conductive line is electrically connected to the vertical structure on the second stack group. A distance between an upper end of the first vertical region and an upper surface of the substrate is greater than a distance between an upper end of the first separation region and an upper surface of the substrate.

公开(公告)号：US20210249397A1

公开(公告)日：2021-08-12

申请号：US17245299

申请日：2021-04-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Hyun Mog PARK ,  Yong Seok KIM ,  Kyung Hwan LEE ,  Jun Hee LIM ,  Jee Hoon HAN

IPC: H01L25/18 ,  H01L23/00 ,  H01L27/11556 ,  H01L27/11582

Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.

公开(公告)号：US20210118902A1

公开(公告)日：2021-04-22

申请号：US16853047

申请日：2020-04-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kohji KANAMORI ,  Shinhwan KANG

IPC: H01L27/11582 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/11565 ,  H01L21/311 ,  H01L21/28 ,  H01L21/02

Abstract: A vertical memory device including gate electrodes on a substrate, the gate electrodes being spaced apart in a first direction and stacked in a staircase arrangement; a channel extending through the gate electrodes in the first direction; a first contact plug extending through a pad of a first gate electrode to contact an upper surface of the first gate electrode, the first contact plug extending through a portion of a second gate electrode, and the second gate electrode being adjacent to the first gate electrode; a first spacer between the first contact plug and sidewalls of the first gate electrode and the second gate electrode facing the first contact plug, the first spacer electrically insulating the first contact plug from the second gate electrode; and a first burying pattern contacting bottom surfaces of the first contact plug and the first spacer, the first burying pattern including an insulating material.

公开(公告)号：US20200381449A1

公开(公告)日：2020-12-03

申请号：US16718498

申请日：2019-12-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Je Suk MOON ,  Seo-Goo KANG ,  Young Hwan SON ,  Kohji KANAMORI ,  Jee Hoon HAN

IPC: H01L27/11582 ,  H01L27/11565

Abstract: A nonvolatile memory device includes a mold structure having a stack of word lines on a substrate and first and second string selection lines on the word lines, a first cutting structure through the mold structure, a second cutting structure through the mold structure, the second cutting structure being spaced apart from the first cutting structure, a channel structure penetrating the mold structure to be connected to the substrate, the channel structure being between the first and second cutting structures, a first cutting line cutting through the first string selection line but not through the second string selection line, the first cutting line being between the first and second cutting structures, and a second cutting line cutting through the second string selection line but not through the first string selection line, the second cutting line being between the second cutting structure and the channel structure.

公开(公告)号：US20200343259A1

公开(公告)日：2020-10-29

申请号：US16562919

申请日：2019-09-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Shinhwan KANG ,  Younghwan SON ,  Haemin LEE ,  Kohji KANAMORI ,  Jeehoon HAN

IPC: H01L27/11582 ,  H01L27/11519 ,  H01L27/11565

Abstract: A vertical semiconductor device may include a stacked structure and a plurality of channel structures. The stacked structure may include insulation layers and gate patterns alternately and repeatedly stacked on a substrate. The stacked structure may extend in a first direction parallel to an upper surface of the substrate. The gate patterns may include at least ones of first gate patterns. The stacked structure may include a sacrificial pattern between the first gate patterns. The channel structures may pass through the stacked structure. Each of the channel structures may extend to the upper surface of the substrate, and each of the channel structures may include a charge storage structure and a channel. Ones of the channel structures may pass through the sacrificial pattern in the stacked structure to the upper surface of the substrate, and may extend to the upper surface of the substrate.

公开(公告)号：US20200219898A1

公开(公告)日：2020-07-09

申请号：US16819907

申请日：2020-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Min-Yeong SONG ,  Shin-Hwan KANG

IPC: H01L27/11582 ,  H01L27/11565 ,  H01L27/11573 ,  H01L27/11575 ,  H01L27/06

Abstract: A vertical memory device includes a lower circuit pattern on a substrate, a plurality of gate electrodes spaced apart from another in a first direction substantially perpendicular to an upper surface of the substrate on the lower circuit pattern, a channel extending through the gate electrodes in the first direction, a memory cell block including a first common source line (CSL) extending in a second direction substantially parallel to the upper surface of the substrate, and a first contact plug connected to the lower circuit pattern and the first CSL and overlapping the first CSL in the first direction.

公开(公告)号：US20200020396A1

公开(公告)日：2020-01-16

申请号：US16243281

申请日：2019-01-09

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kohji KANAMORI ,  Chang-Seok KANG ,  Yong-Seok KIM ,  Kyung-Hwan LEE

IPC: G11C13/00 ,  G11C7/12

Abstract: In a method of writing data in a nonvolatile memory device including a plurality of cell strings, each of the plurality of cell strings includes a plurality of memory cells disposed in a vertical direction. A program target page is divided into a plurality of subpages. The program target page is connected to one of a plurality of wordlines. Each of the plurality of subpages includes memory cells that are physically spaced apart from one another. A program operation is sequentially performed on the plurality of subpages. A program verification operation is performed on the program target page including the plurality of subpages at a time.