公开(公告)号：US11901902B2

公开(公告)日：2024-02-13

申请号：US17696086

申请日：2022-03-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungman Lim ,  Minsu Kim ,  Ahreum Kim

IPC: H03K3/02 ,  H03K3/037 ,  H03K17/687 ,  H03K3/3562

CPC classification number: H03K3/0372 ,  H03K3/3562 ,  H03K17/6872

Abstract: An integrated circuit includes a flip-flop configured to operate in synchronization with a clock signal. The flip-flop includes a multiplexer configured to output an inverted signal of a scan input signal to a first node based on a scan enable signal, or the multiplexer configured to output an inverted signal of a data input signal or a signal having a first level to a first node based on a reset input signal, a master latch configured to latch the signal output through the first node, and to output the latched signal, and a slave latch configured to latch an output signal of the master latch and to output the latched output signal of the master latch.

公开(公告)号：US11901033B2

公开(公告)日：2024-02-13

申请号：US18149302

申请日：2023-01-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jooyong Park ,  Minsu Kim ,  Daeseok Byeon ,  Pansuk Kwak

IPC: G11C29/00 ,  G06F11/20 ,  G11C16/04 ,  G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G11C29/12 ,  G11C29/02 ,  G11C29/52 ,  G11C29/42 ,  G11C29/24

CPC classification number: G11C29/838 ,  G06F11/2094 ,  G11C16/0483 ,  G11C29/44 ,  G11C16/10 ,  G11C16/26 ,  G11C16/349 ,  G11C16/3472 ,  G11C29/02 ,  G11C29/24 ,  G11C29/42 ,  G11C29/4401 ,  G11C29/52 ,  G11C29/70 ,  G11C29/702 ,  G11C29/785 ,  G11C29/789 ,  G11C2029/1204

Abstract: A memory device includes a memory cell array including normal memory cells and redundant memory cells; first page buffers connected to the normal memory cells through first bit lines including a first bit line group and a second bit line group and arranged in a first area corresponding to the first bit lines in a line in a first direction; and second page buffers connected to the redundant memory cells through second bit lines including a third bit line group and a fourth bit line group and arranged in a second area corresponding to the second bit lines in a line in the first direction, wherein, when at least one normal memory cell connected to the first bit line group is determined as a defective cell, normal memory cells connected to the first bit line group are replaced with redundant memory cells connected to the third bit line group.

公开(公告)号：US11670259B2

公开(公告)日：2023-06-06

申请号：US17841719

申请日：2022-06-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Soohyun Moon ,  Kyoungmin Park ,  Minsu Kim ,  Keehyon Park ,  Dongheon Shin ,  Hearyun Jung ,  Dongkyoon Han

IPC: G09G5/10

CPC classification number: G09G5/10 ,  G09G2320/046 ,  G09G2320/0626 ,  G09G2330/022 ,  G09G2330/023 ,  G09G2370/022 ,  G09G2370/16

Abstract: An electronic device includes: a display device, a processor operatively connected to the display device, and a memory operatively connected to the processor. The memory stores one or more instructions that when executed, cause the processor to: determine, as a second screen code value, a code value obtained by reducing a first screen code value corresponding to a luminance value of a screen of the display device by a decrement based on the screen being maintained in a turned on state during a first specific time after a screen-off condition of the display device is satisfied, and change the luminance value of the screen to correspond to the determined second screen code value.

公开(公告)号：US11528018B2

公开(公告)日：2022-12-13

申请号：US16930658

申请日：2020-07-16

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jongwoo Kim ,  Minsu Kim ,  Yonggeol Kim ,  Hyun Lee ,  Hyunchul Hwang

IPC: H03K3/3562 ,  H03K3/037 ,  H03K19/00

Abstract: A flip-flop includes an input switching circuit configured to output an intermediate signal based on an input signal and at least one of a phase of a clock signal or a phase of an inverted clock signal, the phase of the inverted clock signal being opposite to the phase of the clock signal, and block application of a driving voltage to at least one circuit element of the input switching circuit in response to receiving a reset signal representing a reset operation of the flip-flop, and a latch circuit configured to generate an output signal based on the intermediate signal according to the at least one of the phase of the clock signal or the phase of the inverted clock signal.

公开(公告)号：US11487613B2

公开(公告)日：2022-11-01

申请号：US17105821

申请日：2020-11-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Wonjae Shin ,  Nam Hyung Kim ,  Dae-Jeong Kim ,  Do-Han Kim ,  Minsu Kim ,  Deokho Seo ,  Yongjun Yu ,  Changmin Lee ,  Insu Choi

IPC: G11C29/00 ,  G06F11/10 ,  G06F11/16 ,  G06F11/30

Abstract: A method for accessing a memory module includes; encoding first data of a first partial burst length to generate first parities and first cyclic redundancy codes, encoding second data of a second partial burst length to generate second parities and second cyclic redundancy codes, writing the first data and the second data to first memory devices, and writing the first parities, the first cyclic redundancy codes, the second parities, and the second cyclic redundancy codes to a second memory device and a third memory device.

公开(公告)号：US10990463B2

公开(公告)日：2021-04-27

申请号：US16218720

申请日：2018-12-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minsu Kim ,  Jiseok Kang ,  Minsoo Kim ,  Byungjik Kim ,  Wonjae Shin ,  Donghoon Lee ,  Yeonhwa Lee ,  Ho-Young Lee ,  Youjin Jang ,  Insu Choi

IPC: G06F11/07 ,  G06F12/02 ,  G06F12/0804 ,  G06F11/14

Abstract: A semiconductor memory module may include a random access memory, a nonvolatile memory, a buffer memory, and a controller configured to execute a reading operation on the buffer memory in response to an activation of a control signal. The controller may be further configured to execute a flush operation of storing first data, which are stored in the random access memory, in the nonvolatile memory, according to a result of the reading operation.

公开(公告)号：US20200328746A1

公开(公告)日：2020-10-15

申请号：US16845135

申请日：2020-04-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANHEE PARK ,  Jongwoo Kim ,  Minsu Kim

IPC: H03K19/00 ,  H03K17/687

Abstract: An integrated circuit is provided. The integrated circuit includes a power gating circuit configured to receive a power supply voltage from a first power line and to output a first driving voltage to a first virtual power line and a logic circuit electrically connected to the first virtual power line and configured to receive power from the power gating circuit. The power gating circuit includes a first p-type transistor and a first n-type transistor connected in parallel between the first power line and the first virtual power line.

公开(公告)号：US10755018B2

公开(公告)日：2020-08-25

申请号：US16102888

申请日：2018-08-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jong Kyu Ryu ,  Minsu Kim

IPC: G06F17/50 ,  G06F30/392 ,  H01L29/66 ,  H01L27/02 ,  H01L27/118

Abstract: A semiconductor device includes a first standard cell and a second standard cell. A single diffusion break region extending in a first direction is formed in the first standard cell, and a first edge region extending in the first direction and having a maximum cutting depth in a depth direction perpendicular to the first direction is in the first standard cell. A double diffusion break region extending in the first direction is formed in the second standard cell, and a second edge region extending in the first direction and having the maximum cutting depth in the depth direction is formed in the second standard cell.

公开(公告)号：US10371584B2

公开(公告)日：2019-08-06

申请号：US14982802

申请日：2015-12-29

Applicant: Samsung Electronics Co. Ltd.

Inventor： Minsu Kim ,  Kuntak Kim ,  Kiyeon Park ,  Chuleun Yun ,  Jubeam Lee ,  Seyoung Jang ,  Hyojae Cho ,  Bongsu Chun ,  Younghee Ha

IPC: G01K13/00 ,  H04N5/232 ,  H04M1/725

Abstract: A temperature control system of a mobile device is provided. The system includes a memory for storing a set temperature value and a release temperature value, a temperature sensor for sensing an internal temperature of the mobile device; at least one module that emits heat, and a controller. The controller compares the output of the temperature sensor with the set temperature value in a normal mode in order to determine whether the mobile device is overheated, and controls, if the mobile device is overheated, the at least one module to operate in a heat generation suppressing mode, compares the output of the temperature sensor with the release temperature value in the heat generation suppressing mode in order to determine whether to release the heat generation suppressing mode, and executes the normal mode if the heat generation suppressing mode is released according to the comparison result.

公开(公告)号：US10348299B2

公开(公告)日：2019-07-09

申请号：US16001701

申请日：2018-06-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Hyunchul Hwang ,  Minsu Kim

IPC: H03K19/00 ,  G06F1/3237

Abstract: A clock gating circuit includes a first precharge unit charging a first node based on a clock signal, a second precharge unit charging a second node based on the clock signal, a first discharge unit discharging the first node based on the clock signal, a second discharge unit discharging the second node based on the clock signal, a first cross-coupled maintain unit maintaining the first node at a charge state according to a voltage level of the second node, a second cross-coupled maintain unit maintaining the second node at a charge state according to a voltage level of the first node, and a control unit controlling the first and second discharge units to discharge the first node or the second node on the basis of a clock enable signal.