公开(公告)号：US20230245706A1

公开(公告)日：2023-08-03

申请号：US17589789

申请日：2022-01-31

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yi Song ,  Jiahui Yuan ,  Yanjie Wang

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/30

CPC classification number: G11C16/3459 ,  G11C16/3404 ,  G11C16/102 ,  G11C16/26 ,  G11C16/24 ,  G11C16/30

Abstract: In order to decrease the width of threshold voltage distributions of programmed memory cells without unreasonably increasing the time needed to complete programming, a non-volatile memory uses a zone based program speed adjustment. The non-volatile memory starts programming a first set of the non-volatile memory cells until a minimum number of memory cells of the first set of non-volatile memory cells reach a first threshold voltage. In response to the minimum number of memory cells reaching the first threshold voltage, the first set of non-volatile memory cells are categorized into zones/groups based on threshold voltage. The speed of programming is then adjusted differently for each zone/group and programming is completed for the first set of non-volatile memory cells.

公开(公告)号：US20230154541A1

公开(公告)日：2023-05-18

申请号：US17530196

申请日：2021-11-18

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Jiahui Yuan ,  Deepanshu Dutta

IPC: G11C16/14 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04 ,  G11C16/30 ,  G11C7/10

CPC classification number: G11C16/14 ,  G11C16/102 ,  G11C16/26 ,  G11C16/08 ,  G11C16/0433 ,  G11C16/30 ,  G11C7/1048

Abstract: Programming a plurality of non-volatile memory cells includes performing a soft erase process during the programming. The soft erase process includes pre-charging channels of the memory cells and performing an erase operation subsequent to the pre-charging while the channels are at one or more elevated voltages at least partially due to the pre-charging.

公开(公告)号：US20230120352A1

公开(公告)日：2023-04-20

申请号：US17505179

申请日：2021-10-19

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yu-Chung Lien ,  Jiahui Yuan ,  Ohwon Kwon

IPC: G11C16/34 ,  H01L27/11556 ,  H01L27/11582 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26

Abstract: A control circuit connected to non-volatile memory cells applies a programming signal to a plurality of the non-volatile memory cells in order to program the plurality of the non-volatile memory cells to a set of data states. The control circuit performs program verification for the non-volatile memory cells, including applying bit line voltages during program verification based on word line position and data state being verified.

公开(公告)号：US20230056891A1

公开(公告)日：2023-02-23

申请号：US17406224

申请日：2021-08-19

Applicant: SanDisk Technologies LLC

Inventor： Yu-Chung Lien ,  Deepanshu Dutta ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/24 ,  G11C16/04 ,  G11C16/30

Abstract: Apparatuses and techniques are described for controlling a bit line pre-charge voltage in a program operation based on a number of bits per cell, with a goal to reduce peak current consumption. In one aspect, the ramp up of a bit line voltage to an inhibit level is optimized according to the number of bits per cell. The ramp up can involve increasing the bit line voltage from an initial level to a target voltage at a regulated rate, then increasing the bit line voltage from the target voltage to a final voltage at an unregulated rate. In one approach, the regulated ramp rate is less for single-level cell programming compared to multi-level cell programming. The target voltage can also be optimized based on the number of bis per cell.

公开(公告)号：US11139018B1

公开(公告)日：2021-10-05

申请号：US17007442

申请日：2020-08-31

Applicant: SanDisk Technologies LLC

Inventor： Abu Naser Zainuddin ,  Ohwon Kwon ,  Jiahui Yuan

IPC: G11C7/12 ,  G11C11/4074 ,  G11C11/4091 ,  G11C5/14 ,  G11C11/4097 ,  G11C11/4094 ,  G11C16/26 ,  G11C16/04 ,  G11C16/34 ,  G11C16/24 ,  G11C11/56

Abstract: Apparatuses and techniques are described for reducing read time in a memory device. A source voltage signal, Vcelsrc, and a body voltage signal, Vp-well, of a source region and a p-well, respectively, of a substrate of a NAND string are controlled to reduce the channel resistance. Vcelsrc can be temporarily reduced, e.g., provided with a negative voltage kick, while Vp-well is non-decreasing during a read operation. The negative voltage kick decreases a body bias of the NAND string in its channel to reduce the channel resistance and increase the current. The negative voltage kick can be initiated when a bit line clamp transistor is made conductive to allow a current to flow in the NAND string. The magnitude and duration of the negative voltage kick can be adjusted based on various factors.

公开(公告)号：US20210257039A1

公开(公告)日：2021-08-19

申请号：US16790362

申请日：2020-02-13

Applicant: SanDisk Technologies LLC

Inventor： Abhijith Prakash ,  Jiahui Yuan

IPC: G11C16/34 ,  G11C16/04 ,  G11C11/56 ,  G11C5/14

Abstract: Apparatuses and techniques are described for periodically refreshing word line voltages in a block of memory cells based on the susceptibility of the block to read errors. One source of read errors is delayed read disturb which results from a low word line voltage during idle periods of the memory device. In one aspect, periodic refresh operations are optimized based on factors such as a number of bits per cell in the block and number of program-erase (P-E) cycles. For example, at high P-E cycles, the amplitude of a refresh voltage for a single-level cell (SLC) block can be 0 V or lower while the amplitude of a refresh voltage for a multi-level cell (MLC) block can be an intermediate voltage between 0 V and a pass voltage.

公开(公告)号：US09910749B2

公开(公告)日：2018-03-06

申请号：US15191150

申请日：2016-06-23

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Nian Niles Yang ,  Jiahui Yuan ,  Grishma Shah ,  Xinde Hu ,  Lanlan Gu ,  Bin Wu

IPC: G11C16/04 ,  G06F11/20 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16

CPC classification number: G06F11/2094 ,  G06F2201/805 ,  G06F2201/82 ,  G11C8/08 ,  G11C8/14 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/3495 ,  G11C29/025 ,  G11C2029/1202

Abstract: A non-volatile memory system includes a plurality of non-volatile data memory cells arranged into groups of data memory cells, a plurality of select devices connected to the groups of data memory cells, a selection line connected to the select devices, a plurality of data word lines connected to the data memory cells, and one or more control circuits connected to the selection line and the data word lines. The one or more control circuits are configured to determine whether the select devices are corrupted. If the select devices are corrupted, then the one or more control circuits repurpose one of the word lines (e.g., the first data word line closet to the select devices) to be another selection line, thus operating the memory cells connected to the repurposed word line as select devices.

公开(公告)号：US09748267B2

公开(公告)日：2017-08-29

申请号：US15256114

申请日：2016-09-02

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Yanli Zhang ,  Go Shoji ,  Johann Alsmeier ,  Jayavel Pachamuthu ,  Yingda Dong ,  Jiahui Yuan

IPC: H01L21/336 ,  H01L29/66 ,  H01L27/11582 ,  H01L27/11529 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/28 ,  H01L27/11556 ,  H01L29/788

CPC classification number: H01L27/11582 ,  H01L21/28282 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/1157 ,  H01L29/7883

Abstract: A NAND memory cell region of a NAND device includes a conductive source line that extends substantially parallel to a major surface of a substrate, a first semiconductor channel that extends substantially perpendicular to a major surface of the substrate, and a second semiconductor channel that extends substantially perpendicular to the major surface of the substrate. At least one of a bottom portion and a side portion of the first semiconductor channel contacts the conductive source line and at least one of a bottom portion and a side portion of the second semiconductor channel contacts the conductive source line.

公开(公告)号：US12293797B2

公开(公告)日：2025-05-06

申请号：US18355343

申请日：2023-07-19

Applicant: SanDisk Technologies LLC

Inventor： Longju Liu ,  Sarath Puthenthermadam ,  Jiahui Yuan

IPC: G11C16/10 ,  G11C16/34

Abstract: An apparatus is provided that includes a control circuit coupled to a plurality of non-volatile memory cells. The control circuit is configured to perform a program-verify iteration on a first set of the non-volatile memory cells in a plurality of program loops, determine that the first set of the non-volatile memory cells passes verification to a particular programmed state in a first number of program loops, determine a first voltage based on the first number of program loops, add an adaptive voltage offset to the first voltage to obtain a second voltage, and program a second set of the non-volatile memory cells in a plurality of program loops using the second voltage. The adaptive voltage offset varies as a function of temperature.

公开(公告)号：US12160989B2

公开(公告)日：2024-12-03

申请号：US17716698

申请日：2022-04-08

Applicant: SANDISK TECHNOLOGIES LLC

Inventor： Ramy Nashed Bassely Said ,  Raghuveer S. Makala ,  Jiahui Yuan ,  Senaka Kanakamedala

IPC: H01L23/48 ,  H01L23/52 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/35 ,  H10B43/10 ,  H10B43/27 ,  H10B43/35

Abstract: A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers, memory openings vertically extending through the alternating stack, memory opening fill structures located within a respective one of the memory openings, and a drain-select-level isolation structure. One of the insulating layers is a composite insulating layer including an insulating-material-containing sublayer consisting essentially of an insulating material and an etch stop dielectric material sublayer having a material composition that is different from the insulating material. The etch stop dielectric material sublayer can be employed as an etch stop structure during formation of the drain-select-level isolation structure through drain-select-level electrically conductive layers.