公开(公告)号：US09966462B2

公开(公告)日：2018-05-08

申请号：US15208466

申请日：2016-07-12

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Woochul Jeon ,  Chun-Li Liu ,  Ali Salih

IPC: H01L29/15 ,  H01L29/778 ,  H01L29/20 ,  H01L29/417 ,  H01L29/06 ,  H01L29/40 ,  H01L27/088 ,  H01L29/16 ,  H01L23/495

CPC classification number: H01L29/778 ,  H01L23/4952 ,  H01L23/49537 ,  H01L23/585 ,  H01L27/0883 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/1066 ,  H01L29/16 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H01L29/42316

Abstract: Implementations of semiconductor devices may include: a plurality of drain fingers and a plurality of source fingers interdigitated with one another; at least one gate; and at gate bus formed to completely surround the plurality of drain fingers and the plurality of source fingers; wherein the gate bus is mechanically and electrically coupled to the at least one gate.

公开(公告)号：US20180005927A1

公开(公告)日：2018-01-04

申请号：US15690773

申请日：2017-08-30

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L23/00 ,  H01L23/498 ,  H01L25/18 ,  H01L23/373 ,  H01L29/20 ,  H01L29/16

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L29/16 ,  H01L29/2003 ,  H01L2224/32145 ,  H01L2224/37099 ,  H01L2224/40105 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/49112 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1306 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

公开(公告)号：US09780019B2

公开(公告)日：2017-10-03

申请号：US15207626

申请日：2016-07-12

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L25/18 ,  H01L23/00 ,  H01L23/498 ,  H01L29/20 ,  H01L29/16 ,  H01L23/373

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/4952 ,  H01L23/49524 ,  H01L23/49562 ,  H01L23/49861 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/18 ,  H01L29/16 ,  H01L29/2003 ,  H01L2224/37099 ,  H01L2224/40105 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48105 ,  H01L2224/48145 ,  H01L2224/48245 ,  H01L2224/49112 ,  H01L2224/49176 ,  H01L2224/49177 ,  H01L2224/73221 ,  H01L2924/00014 ,  H01L2924/1203 ,  H01L2924/1306 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012 ,  H01L2224/85399

Abstract: A semiconductor component includes a support having a lead integrally formed thereto. An insulated metal substrate is mounted to a surface of the support and a semiconductor chip is mounted to the insulated metal substrate. A III-N based semiconductor chip is mounted to the insulated metal substrate, where the III-N based semiconductor chip has a gate bond pad, a drain bond pad, and a source bond pad. A silicon based semiconductor chip is mounted to the III-N based semiconductor chip. In accordance with an embodiment the silicon based semiconductor chip includes a device having a gate bond pad, a drain bond pad, and a source bond pad. The drain bond pad of the III-N based semiconductor chip may be bonded to the substrate or to a lead. In accordance with another embodiment, the silicon based semiconductor chip is a diode.

公开(公告)号：US09754931B2

公开(公告)日：2017-09-05

申请号：US14808627

申请日：2015-07-24

Applicant: Semiconductor Components Industries, LLC

Inventor： Woochul Jeon ,  Joe Fulton ,  Chun-Li Liu

IPC: H01L29/66 ,  H01L27/06 ,  H01L29/778

CPC classification number: H01L27/0629 ,  H01L29/778 ,  H03K17/6871 ,  H03K2017/6875 ,  H03K2217/0036

Abstract: A circuit can include a transistor coupled to a resistor or a diode. In an embodiment, the circuit can include a pair of transistors arranged in a cascode configuration, and each of the transistors can have a corresponding component connected in parallel. In a particular embodiment, the components can be resistors, and in another particular, embodiment, the components can be diodes. The circuit can have less on-state resistance as compared to a circuit in which only one of the components is used, and reduces the off-state voltage on the gate of a high-side transistor. An integrated circuit can include a high electron mobility transistor structure and a resistor, a diode, a pair of resistors, or a pair of diodes.

公开(公告)号：US09741711B2

公开(公告)日：2017-08-22

申请号：US14853729

申请日：2015-09-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Balaji Padmanabhan ,  Prasad Venkatraman ,  Zia Hossain ,  Chun-Li Liu ,  Woochul Jeon ,  Jason McDonald

IPC: H01L29/66 ,  H01L21/70 ,  H01L27/06 ,  H01L27/02 ,  H01L23/367 ,  H01L29/417 ,  H01L29/778 ,  H01L29/10 ,  H01L21/8258 ,  H01L21/74 ,  H01L29/872 ,  H01L23/48 ,  H01L29/861 ,  H01L29/20

CPC classification number: H01L27/0629 ,  H01L21/743 ,  H01L21/8258 ,  H01L23/3677 ,  H01L23/481 ,  H01L27/0255 ,  H01L27/0266 ,  H01L27/0688 ,  H01L29/1087 ,  H01L29/2003 ,  H01L29/41766 ,  H01L29/7783 ,  H01L29/861 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/00

Abstract: In one embodiment, a cascode rectifier structure includes a group III-V semiconductor structure includes a heterostructure disposed on a semiconductor substrate. A first current carrying electrode and a second current carrying electrode are disposed adjacent a major surface of the heterostructure and a control electrode is disposed between the first and second current carrying electrode. A rectifier device is integrated with the group III-V semiconductor structure and is electrically connected to the first current carrying electrode and to a third electrode. The control electrode is further electrically connected to the semiconductor substrate and the second current path is generally perpendicular to a primary current path between the first and second current carrying electrodes.

公开(公告)号：US20170221752A1

公开(公告)日：2017-08-03

申请号：US15487517

申请日：2017-04-14

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Balaji Padmanabhan ,  Ali Salih ,  Peter Moens

IPC: H01L21/76 ,  H01L21/763 ,  H01L21/762 ,  H01L29/20 ,  H01L29/06

CPC classification number: H01L29/7827 ,  H01L21/743 ,  H01L21/746 ,  H01L21/7605 ,  H01L21/76224 ,  H01L21/763 ,  H01L21/76898 ,  H01L29/0607 ,  H01L29/0649 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/4175 ,  H01L29/66318 ,  H01L29/66462 ,  H01L29/66666 ,  H01L29/7786

Abstract: In accordance with an embodiment, a semiconductor component includes a plurality of layers of compound semiconductor material over a body of semiconductor material and first and second filled trenches extending into the plurality of layers of compound semiconductor material. The first trench has first and second sidewalls and a floor and a first dielectric liner over the first and second sidewalls and the second trench has first and second sidewalls and a floor and second dielectric liner over the first and second sidewalls of the second trench.

公开(公告)号：US20170025335A1

公开(公告)日：2017-01-26

申请号：US15202765

申请日：2016-07-06

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Balaji Padmanabhan ,  Mingjiao Liu

IPC: H01L23/495 ,  H01L23/00 ,  H01L29/45

CPC classification number: H01L23/49575 ,  H01L23/3735 ,  H01L23/49524 ,  H01L23/49531 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49568 ,  H01L24/73 ,  H01L25/072 ,  H01L29/2003 ,  H01L33/62 ,  H01L2224/40 ,  H01L2224/40245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48245 ,  H01L2224/49111 ,  H01L2224/73221 ,  H01L2224/73265 ,  H01L2924/00014 ,  H01L2224/37099

Abstract: In accordance with an embodiment, a semiconductor component is provided that includes a leadframe having a device receiving area, one or more leadframe leads and at least one insulated metal substrate bonded to a first portion of the device receiving area. A first semiconductor device is mounted to a first insulated metal substrate, the first semiconductor device configured from a III-N semiconductor material. A first electrical interconnect is coupled between the first current carrying terminal of the first semiconductor device and a second portion of the die receiving area. In accordance with another embodiment, method includes providing a first semiconductor chip comprising a III-N semiconductor substrate material and a second semiconductor chip comprising a silicon based semiconductor substrate. The first semiconductor chip is mounted on a first substrate and the second semiconductor chip on a second substrate. The first semiconductor chip is electrically coupled to the second semiconductor chip.

Abstract translation: 根据实施例，提供了半导体部件，其包括具有器件接收区域的引线框架，一个或多个引线框架引线以及结合到器件接收区域的第一部分的至少一个绝缘金属衬底。 第一半导体器件安装到第一绝缘金属衬底，第一半导体器件由III-N半导体材料构成。 第一电互连耦合在第一半导体器件的第一载流端子和管芯接收区域的第二部分之间。 根据另一实施例，方法包括提供包括III-N半导体衬底材料的第一半导体芯片和包括硅基半导体衬底的第二半导体芯片。 第一半导体芯片安装在第一基板上，第二半导体芯片安装在第二基板上。 第一半导体芯片电耦合到第二半导体芯片。

公开(公告)号：US20140264449A1

公开(公告)日：2014-09-18

申请号：US14162082

申请日：2014-01-23

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： John Michael Parsey, JR. ,  Chun-Li Liu ,  Balaji Padmanabhan ,  Ali Salih

IPC: H01L29/06 ,  H01L29/66 ,  H01L29/778

CPC classification number: H01L29/0653 ,  H01L21/7624 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/404 ,  H01L29/66462 ,  H01L29/7786 ,  H01L29/7787

Abstract: In one embodiment, a HEMT semiconductor device includes an isolation region that may include oxygen wherein the isolation region may extend thorough an ALGaN and GaN layer into an underlying layer.

Abstract translation: 在一个实施例中，HEMT半导体器件包括可以包括氧的隔离区，其中隔离区域可以将ALGaN和GaN层延伸到下面的层中。

公开(公告)号：US10930524B2

公开(公告)日：2021-02-23

申请号：US16406899

申请日：2019-05-08

Applicant: SEMICONDUCTOR COMPONENTS INDUSTRIES, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Mingjiao Liu

IPC: H01L21/48 ,  H01L29/20 ,  H01L23/00 ,  H01L21/52 ,  H01L23/492 ,  H01L23/498 ,  H01L25/065 ,  H01L23/495

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. A first electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a first lead. A second electrical interconnect is coupled between the control terminal of the semiconductor device and a second lead.

公开(公告)号：US10388539B2

公开(公告)日：2019-08-20

申请号：US15202917

申请日：2016-07-06

Applicant: Semiconductor Components Industries, LLC

Inventor： Chun-Li Liu ,  Ali Salih ,  Mingjiao Liu

IPC: H01L21/48 ,  H01L21/52 ,  H01L23/00 ,  H01L29/20 ,  H01L23/492 ,  H01L23/495 ,  H01L23/498

Abstract: In accordance with an embodiment, a semiconductor component includes a support having a side in which a device receiving structure and an interconnect structure are formed and a side from which a plurality of leads extends. A semiconductor device having a control terminal and first and second current carrying terminals and configured from a III-N semiconductor material is mounted to the device receiving structure. The control terminal of the first electrical interconnect is coupled to a first lead by a first electrical interconnect. A second electrical interconnect is coupled between the first current carrying terminal of the semiconductor device and a second lead. The second current carrying terminal of the first semiconductor device is coupled to the device receiving structure or to the interconnect structure.