公开(公告)号：US10223960B2

公开(公告)日：2019-03-05

申请号：US15684085

申请日：2017-08-23

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Kei Takahashi

IPC: G09G3/36 ,  G09G3/20 ,  H01L27/32 ,  H03F3/45 ,  G09G3/3275 ,  H03F3/195 ,  H03F3/30 ,  H03F3/68 ,  H01L27/12 ,  G09G5/02

Abstract: The transmission delay time of a receiver for receiving a differential signal is reduced. A first amplifier circuit is provided in an input stage of the receiver, and a second amplifier circuit is provided in an output stage of the receiver. The first amplifier circuit is a differential input, differential output amplifier circuit. The second amplifier circuit is a differential input, single-ended output amplifier circuit. A first power supply voltage and a second power supply voltage are input as a high-level power supply voltage and a low-level power supply voltage to the first amplifier circuit and the second amplifier circuit, respectively. The withstand voltage of transistors of a differential pair of the first amplifier circuit is higher than the withstand voltage of another transistor included in the first amplifier circuit and a transistor included in the second amplifier circuit.

公开(公告)号：US09576994B2

公开(公告)日：2017-02-21

申请号：US14837040

申请日：2015-08-27

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Hiroki Inoue ,  Yoshiyuki Kurokawa ,  Takayuki Ikeda ,  Yuki Okamoto

IPC: H01L27/146 ,  H01L29/786 ,  H01L29/10

CPC classification number: H01L27/14612 ,  H01L27/14632 ,  H01L27/14643 ,  H01L29/7869

Abstract: An imaging device capable of obtaining high-quality imaging data is provided. The imaging device includes a first circuit and a second circuit. The first circuit includes a photoelectric conversion element, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, a first capacitor, a second capacitor, and a third capacitor. The second circuit includes an eighth transistor. Variation in threshold voltage of an amplifier transistor (the fifth transistor) included in the first circuit can be compensated.

Abstract translation: 提供能够获得高质量成像数据的成像装置。 成像装置包括第一电路和第二电路。 第一电路包括光电转换元件，第一晶体管，第二晶体管，第三晶体管，第四晶体管，第五晶体管，第六晶体管，第七晶体管，第一电容器，第二电容器和第三电容器。 第二电路包括第八晶体管。 可以补偿包括在第一电路中的放大器晶体管（第五晶体管）的阈值电压的变化。

公开(公告)号：US09525051B2

公开(公告)日：2016-12-20

申请号：US14740688

申请日：2015-06-16

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G11C11/00 ,  H01L29/66 ,  G11C11/404 ,  G11C11/405 ,  G11C16/04 ,  H01L27/115 ,  H01L27/12 ,  H01L27/108 ,  G11C16/08 ,  G11C16/24 ,  H01L29/786 ,  H01L21/02 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  G11C11/4091

CPC classification number: H01L27/1052 ,  G11C11/404 ,  G11C11/405 ,  G11C11/4091 ,  G11C16/0408 ,  G11C16/08 ,  G11C16/24 ,  H01L21/02565 ,  H01L21/02631 ,  H01L21/425 ,  H01L21/441 ,  H01L21/477 ,  H01L27/108 ,  H01L27/11521 ,  H01L27/11526 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1222 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1255 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.

公开(公告)号：US09472293B2

公开(公告)日：2016-10-18

申请号：US14990908

申请日：2016-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/08 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/045 ,  G11C16/08 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

公开(公告)号：US20160203871A1

公开(公告)日：2016-07-14

申请号：US14990908

申请日：2016-01-08

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shuhei Nagatsuka ,  Hiroki Inoue ,  Takahiko Ishizu ,  Takanori Matsuzaki ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC: G11C16/24

CPC classification number: G11C16/24 ,  G11C11/5642 ,  G11C16/04 ,  G11C16/0408 ,  G11C16/0441 ,  G11C16/045 ,  G11C16/08 ,  H01L27/1156 ,  H01L27/1225 ,  H01L29/7869 ,  H01L29/78696

Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.

Abstract translation: 从具有使用硅的晶体管的存储单元和使用氧化物半导体的晶体管读取多电平数据，而不用根据多电平数据的电平数来切换用于读取多电平数据的信号。 位线的电位被预充电，位线的电荷通过用于写入数据的晶体管放电，并且由放电改变的位线的电位被读取为多电平数据。 通过这样的结构，可以通过仅读取数据的信号的一次切换来读取对应于保持在晶体管的栅极中的数据的电位。

公开(公告)号：US09007813B2

公开(公告)日：2015-04-14

申请号：US13795244

申请日：2013-03-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Toshihiko Saito ,  Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

IPC: G11C11/24 ,  H01L29/78 ,  G11C11/403 ,  G11C11/406 ,  G11C16/04 ,  H01L27/115 ,  H01L27/12

CPC classification number: H01L29/78 ,  G11C11/403 ,  G11C11/406 ,  G11C16/0416 ,  G11C2211/4065 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

Abstract: A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.

Abstract translation: 一种半导体器件包括多个包括第一晶体管和第二晶体管的存储单元，包括放大器电路和开关元件的读取电路以及刷新控制电路。 第一通道形成区域和第二通道形成区域包含不同的材料作为它们各自的主要成分。 第一栅电极电连接到第二源电极和第二漏极之一。 第二源极和第二漏极中的另一个电连接到放大器电路的一个输入端。 放大器电路的输出端子通过开关元件连接到第二源电极和第二漏电极中的另一个。 刷新控制电路被配置为控制开关元件是打开还是关闭。

公开(公告)号：US08791461B2

公开(公告)日：2014-07-29

申请号：US14037778

申请日：2013-09-26

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki Atsumi ,  Hiroki Inoue

IPC: H01L29/10

CPC classification number: H01L21/02683 ,  H01L21/02532 ,  H01L21/2026 ,  H01L27/1255 ,  H01L27/1285 ,  H01L27/1296 ,  H01L28/40

Abstract: In a semiconductor device including a digital circuit portion and an analog circuit portion having a capacitor portion provided over a substrate, the capacitor portion is provided with a first wiring, a second wiring and a plurality of blocks each having a plurality of capacitor elements. Further, each the plurality of capacitor elements provided in each block has a semiconductor film having a first impurity region and a plurality of second impurity regions provided apart with the first impurity region interposed therebetween, and a conductive film provided over the first impurity region with an insulating film therebetween. A capacitor is formed from the first impurity region, the insulating film, and the conductive film.

Abstract translation: 在包括数字电路部分和具有设置在基板上的电容器部分的模拟电路部分的半导体器件中，电容器部分设置有第一布线，第二布线和多个具有多个电容器元件的块。 此外，设置在每个块中的多个电容器元件中的每一个具有半导体膜，该半导体膜具有第一杂质区和设置有分隔开第一杂质区的多个第二杂质区，并且在第一杂质区上设置有导电膜， 绝缘膜。 由第一杂质区，绝缘膜和导电膜形成电容器。

公开(公告)号：US08542004B2

公开(公告)日：2013-09-24

申请号：US13683863

申请日：2012-11-21

Applicant: Semiconductor Energy Laboratory Co. Ltd.

Inventor： Hiroki Inoue ,  Kiyoshi Kato ,  Takanori Matsuzaki ,  Shuhei Nagatsuka

IPC: G01R19/00

CPC classification number: G11C11/24 ,  G11C11/403 ,  G11C11/405 ,  H01L27/1052 ,  H01L27/11521 ,  H01L27/1225

Abstract: An object is to provide a semiconductor device with a novel structure in which stored data can be held even when power is not supplied, and the number of times of writing is not limited. The semiconductor device is formed using a wide gap semiconductor and includes a potential change circuit which selectively applies a potential either equal to or different from a potential of a bit line to a source line. Thus, power consumption of the semiconductor device can be sufficiently reduced.

Abstract translation: 目的在于提供具有新颖结构的半导体器件，其中即使在不提供电力的情况下也可以保持存储的数据，并且写入的次数不受限制。 半导体器件使用宽间隙半导体形成，并且包括电位改变电路，其选择性地将与位线的电位等于或不同的电位施加到源极线。 因此，可以充分降低半导体器件的功耗。

公开(公告)号：US12132334B2

公开(公告)日：2024-10-29

申请号：US17292218

申请日：2019-11-12

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Kei Takahashi ,  Yuki Okamoto ,  Minato Ito ,  Takahiko Ishizu ,  Hiroki Inoue ,  Shunpei Yamazaki

IPC: H02J7/00 ,  H01M10/42 ,  H01M10/44 ,  H03K3/0231 ,  H03K17/082

CPC classification number: H02J7/00304 ,  H01M10/4264 ,  H01M10/44 ,  H02J7/0031 ,  H03K3/0231 ,  H03K17/0822

Abstract: A semiconductor device with reduced power consumption is provided. The semiconductor device includes a node ND1, a node ND2, a resistor, a capacitor, and a comparison circuit. The resistor is electrically connected in series between one of a positive electrode and a negative electrode of a secondary battery and a first terminal. The resistor has a function of converting current flowing between the one of the positive electrode and the negative electrode of the secondary battery and the first terminal into a first voltage. The first voltage is added to a voltage of the node ND2 through the capacitor. The comparison circuit has a function of comparing a voltage of the node ND1 and the voltage of the node ND2. The comparison circuit outputs a signal that notifies detection of overcurrent when the voltage of the node ND2 is higher than the voltage of the node ND1.

公开(公告)号：US12062764B2

公开(公告)日：2024-08-13

申请号：US17420536

申请日：2020-01-06

Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.

Inventor： Ryota Tajima ,  Kei Takahashi ,  Hiroki Inoue ,  Munehiro Kozuma ,  Takahiro Fukutome

IPC: H01M10/44 ,  G01R31/367 ,  H01M10/48 ,  H02J7/00

CPC classification number: H01M10/443 ,  G01R31/367 ,  H01M10/486 ,  H02J7/007182 ,  H02J7/007194

Abstract: A semiconductor device that inhibits deterioration of a secondary battery is provided. The semiconductor device includes a secondary battery module and a first circuit. The secondary battery module includes a secondary battery and a sensor. The first circuit includes a variable resistor. The sensor has a function of measuring a temperature of the secondary battery. The first circuit has a function of judging the charge voltage of the secondary battery and outputting a first result; a function of judging the temperature of the secondary battery measured by the sensor and outputting a second result; a function of determining the magnitude of the variable resistor on the basis of the first result and the second result; a function of discharging the charge voltage through the variable resistor; and a function of stopping discharge when the charge voltage reaches a specified voltage.