公开(公告)号：US20180182899A1

公开(公告)日：2018-06-28

申请号：US15900845

申请日：2018-02-21

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Hideomi SUZAWA ,  Sachiaki TEZUKA ,  Tetsuhiro TANAKA ,  Toshiya ENDO ,  Mitsuhiro ICHIJO

IPC: H01L29/786 ,  H01L29/66 ,  H01L21/8258 ,  H01L29/423 ,  H01L27/12 ,  H01L27/092 ,  H01L27/06 ,  H01L29/49

CPC classification number: H01L29/78648 ,  H01L21/8258 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/1207 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78651 ,  H01L29/7869 ,  H01L29/78696

Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.

公开(公告)号：US20180138212A1

公开(公告)日：2018-05-17

申请号：US15811879

申请日：2017-11-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Kiyoshi KATO ,  Yuta ENDO ,  Ryo TOKUMARU

IPC: H01L27/12 ,  H01L29/786 ,  H01L27/108 ,  H01L29/10 ,  H01L21/02 ,  H01L21/4757 ,  H01L21/443

CPC classification number: H01L27/1225 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/443 ,  H01L21/465 ,  H01L21/47573 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/1255 ,  H01L27/1262 ,  H01L29/1054 ,  H01L29/42384 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: A semiconductor device having favorable electric characteristics is provided. The semiconductor device includes a first transistor and second transistor. The first transistor includes a first conductor over a substrate; a first insulator thereover; a first oxide thereover; a second insulator over thereover; a second conductor including a side surface substantially aligned with a side surface of the second insulator and being over the second insulator; a third insulator including a side surface substantially aligned with a side surface of the second conductor and being over the second conductor; a fourth insulator in contact with a side surface of the second insulator, a side surface of the second conductor, and a side surface of the third insulator; and a fifth insulator in contact with the first oxide and the fourth insulator. The second transistor includes a third conductor; a fourth conductor at least part of which overlaps with the third conductor; and a second oxide between the third conductor and the fourth conductor. The third conductor and the fourth conductor are electrically connected to the first conductor.

公开(公告)号：US20180090618A1

公开(公告)日：2018-03-29

申请号：US15823680

申请日：2017-11-28

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO ,  Yoko TSUKAMOTO

IPC: H01L29/786 ,  H01L29/423

CPC classification number: H01L29/7869 ,  H01L29/42392 ,  H01L29/78696

Abstract: To provide a miniaturized transistor having highly stable electrical characteristics. Furthermore, also in a semiconductor device including the transistor, high performance and high reliability are achieved. The transistor includes, over a substrate, a conductor, an oxide semiconductor, and an insulator. The oxide semiconductor includes a first region and a second region. The resistance of the second region is lower than that of the first region. The entire surface of the first region in the oxide semiconductor is surrounded in all directions by the conductor with the insulator interposed therebetween.

公开(公告)号：US20170278976A1

公开(公告)日：2017-09-28

申请号：US15619670

申请日：2017-06-12

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Kosei NODA ,  Yuta ENDO ,  Toshinari SASAKI

IPC: H01L29/786 ,  H01L29/417

CPC classification number: H01L29/7869 ,  H01L29/41733

Abstract: A semiconductor device including the following components and a manufacturing method of the semiconductor device are provided. The semiconductor device includes a substrate; an oxide semiconductor layer over the substrate; a source electrode and a drain electrode whose end portion has a taper angle and whose upper end portion has a curved surface, the source electrode and the drain electrode being electrically connected to the oxide semiconductor layer; a gate insulating layer being in contact with a part of the oxide semiconductor layer and covering the oxide semiconductor layer, the source electrode, and the drain electrode; and a gate electrode overlapping with the oxide semiconductor layer and being over the gate insulating layer.

公开(公告)号：US20170236942A1

公开(公告)日：2017-08-17

申请号：US15584242

申请日：2017-05-02

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA

IPC: H01L29/786 ,  H01L21/02 ,  H01L21/477

CPC classification number: H01L29/66969 ,  H01L21/02 ,  H01L21/02112 ,  H01L21/02403 ,  H01L21/28 ,  H01L21/425 ,  H01L21/477 ,  H01L29/42384 ,  H01L29/518 ,  H01L29/78618 ,  H01L29/7869

Abstract: A semiconductor device is manufactured using a transistor in which an oxide semiconductor is included in a channel region and variation in electric characteristics due to a short-channel effect is less likely to be caused. The semiconductor device includes an oxide semiconductor film having a pair of oxynitride semiconductor regions including nitrogen and an oxide semiconductor region sandwiched between the pair of oxynitride semiconductor regions, a gate insulating film, and a gate electrode provided over the oxide semiconductor region with the gate insulating film positioned therebetween. Here, the pair of oxynitride semiconductor regions serves as a source region and a drain region of the transistor, and the oxide semiconductor region serves as the channel region of the transistor.

公开(公告)号：US20170062192A1

公开(公告)日：2017-03-02

申请号：US15234347

申请日：2016-08-11

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Masashi OOTA ,  Takuya KAWATA ,  Yasumasa YAMANE ,  Yuta ENDO

IPC: H01J37/34 ,  C23C14/35 ,  H01L29/786 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01J37/3405 ,  C23C14/08 ,  C23C14/345 ,  C23C14/35 ,  C23C14/352 ,  C23C14/56 ,  C23C14/564 ,  H01J37/3435 ,  H01J37/3452 ,  H01L21/02565 ,  H01L27/1225 ,  H01L29/66969 ,  H01L29/78648 ,  H01L29/7869 ,  H01L29/78696

Abstract: An oxide with high crystallinity is provided. An oxide having a crystal structure with few defects is provided. An oxide with a low density of defect states is provided. An oxide with a low impurity concentration is provided. A film forming apparatus capable of forming a film of the above-described oxide can be provided. The film forming apparatus includes a target holder, a substrate holder, a first power source, and a second power source. The target holder is electrically connected to the first power source, the substrate holder is electrically connected to the second power source, and the second power source is configured to apply a potential that is higher than a ground potential.

Abstract translation: 提供了高结晶度的氧化物。 提供具有缺陷少的晶体结构的氧化物。 提供了具有低密度缺陷状态的氧化物。 提供了具有低杂质浓度的氧化物。 可以提供能够形成上述氧化物的膜的成膜装置。 成膜设备包括目标保持器，衬底保持器，第一电源和第二电源。 靶保持器电连接到第一电源，衬底保持器电连接到第二电源，并且第二电源被配置为施加高于地电位的电位。

公开(公告)号：US20160087105A1

公开(公告)日：2016-03-24

申请号：US14853542

申请日：2015-09-14

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shinya SASAGAWA ,  Akihisa SHIMOMURA ,  Katsuaki TOCHIBAYASHI ,  Yuta ENDO ,  Shunpei YAMAZAKI

IPC: H01L29/786 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L29/7869 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/31144 ,  H01L21/32136 ,  H01L21/32139 ,  H01L27/1225 ,  H01L29/78648

Abstract: A method for manufacturing a semiconductor device, including the steps of forming a semiconductor over a substrate; forming a first conductor over the semiconductor; forming a first insulator over the first conductor; forming a resist over the first insulator; performing light exposure and development on the resist to make a second region and a third region remain and expose part of the first insulator; applying a bias in a direction perpendicular to a top surface of the substrate and generating plasma using a gas containing carbon and halogen; and depositing and etching an organic substance with the plasma. The etching rate of the organic substance is higher than the deposition rate of the organic substance in an exposed part of the first insulator, and the deposition rate of the organic substance is higher than the etching rate of the organic substance in a side surface of the second region.

Abstract translation: 一种制造半导体器件的方法，包括在衬底上形成半导体的步骤; 在半导体上形成第一导体; 在所述第一导体上形成第一绝缘体; 在第一绝缘体上形成抗蚀剂; 在抗蚀剂上进行曝光和显影以使第二区域和第三区域保持并暴露第一绝缘体的部分; 在垂直于衬底的顶表面的方向施加偏压并使用含有碳和卤素的气体产生等离子体; 并用等离子体沉积和蚀刻有机物质。 有机物的蚀刻速度高于第一绝缘体的露出部分中的有机物质的沉积速度，并且有机物质的沉积速度高于有机物的侧表面中的有机物质的蚀刻速率 第二区。

公开(公告)号：US20160064505A1

公开(公告)日：2016-03-03

申请号：US14935553

申请日：2015-11-09

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Yuta ENDO ,  Toshinari SASAKI ,  Kosei NODA ,  Hitomi SATO ,  Yuhei SATO

IPC: H01L29/49 ,  H01L21/288 ,  H01L21/28 ,  H01L29/66 ,  H01L29/423

CPC classification number: H01L29/4908 ,  H01L21/28088 ,  H01L21/288 ,  H01L27/1225 ,  H01L29/42384 ,  H01L29/66742 ,  H01L29/7869

Abstract: To manufacture a transistor whose threshold voltage is controlled without using a backgate electrode, a circuit for controlling the threshold voltage, and an impurity introduction method. To manufacture a semiconductor device having favorable electrical characteristics, high reliability, and low power consumption using the transistor. A gate electrode including a tungsten oxide film whose composition is controlled is used. The composition or the like is adjusted by a film formation method of the tungsten oxide film, whereby the work function can be controlled. By using the tungsten oxide film whose work function is controlled as part of the gate electrode, the threshold of the transistor can be controlled. Using the transistor whose threshold voltage is controlled, a semiconductor device having favorable electrical characteristics, high reliability, and low power consumption can be manufactured.

Abstract translation: 制造在不使用背栅电极的情况下控制阈值电压的晶体管，用于控制阈值电压的电路和杂质导入方法。 使用晶体管制造具有良好的电特性，高可靠性和低功耗的半导体器件。 使用包含其组成被控制的氧化钨膜的栅电极。 通过氧化钨膜的成膜方法调整组合物等，由此可以控制功函数。 通过使用功函数被控制为栅电极的一部分的氧化钨膜，可以控制晶体管的阈值。 通过使用阈值电压被控制的晶体管，可以制造具有良好的电特性，高可靠性和低功耗的半导体器件。

公开(公告)号：US20150123122A1

公开(公告)日：2015-05-07

申请号：US14534220

申请日：2014-11-06

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Shunpei YAMAZAKI ,  Yuta ENDO

IPC: H01L29/786 ,  H01L23/00 ,  H01L21/66 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L22/10 ,  H01L23/564 ,  H01L29/66742 ,  H01L29/66969 ,  H01L29/78606 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An object of an embodiment of the present invention is to manufacture a highly-reliable semiconductor device comprising a transistor including an oxide semiconductor, in which change of electrical characteristics is small. In the transistor including an oxide semiconductor, oxygen-excess silicon oxide (SiOX (X>2)) is used for a base insulating layer of a top-gate structure or for a protective insulating layer of a bottom-gate structure. By using the oxygen-excess silicon oxide, oxygen is discharged from the insulating layer, and oxygen deficiency of an oxide semiconductor layer and the interface state density between the oxide semiconductor layer and the base insulating layer or the protective insulating layer can be reduced, so that the highly-reliable semiconductor device in which change of electrical characteristics is small can be manufactured.

Abstract translation: 本发明的一个实施例的目的是制造一种包括氧化物半导体的晶体管的高度可靠的半导体器件，其中电特性的变化小。 在包括氧化物半导体的晶体管中，氧过剩氧化硅（SiOX（X> 2））用于顶栅结构的基极绝缘层或底栅结构的保护绝缘层。 通过使用氧过剩的氧化硅，从绝缘层排出氧，氧化物半导体层的氧缺乏和氧化物半导体层与基底绝缘层或保护绝缘层之间的界面态密度可以降低，因此 可以制造电特性变化小的高可靠性的半导体装置。

公开(公告)号：US20230371286A1

公开(公告)日：2023-11-16

申请号：US18225186

申请日：2023-07-24

Applicant: Semiconductor Energy Laboratory Co., Ltd.

Inventor： Tomoaki ATSUMI ,  Shuhei NAGATSUKA ,  Tamae MORIWAKA ,  Yuta ENDO

IPC: H10B69/00 ,  H01L29/786 ,  H01L27/06 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/408 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

CPC classification number: H10B69/00 ,  H01L29/7869 ,  H01L27/0688 ,  G11C7/16 ,  G11C8/14 ,  G11C11/403 ,  G11C11/4085 ,  H10B41/20 ,  H10B41/70 ,  G11C11/24 ,  H01L29/24

Abstract: [Problem] To provide a semiconductor device suitable for miniaturization. To provide a highly reliable semiconductor device. To provide a semiconductor device with improved operating speed.
[Solving Means] A semiconductor device including a memory cell including first to cth (c is a natural number of 2 or more) sub memory cells, wherein: the jth sub memory cell includes a first transistor, a second transistor, and a capacitor; a first semiconductor layer included in the first transistor and a second semiconductor layer included in the second transistor include an oxide semiconductor; one of terminals of the capacitor is electrically connected to a gate electrode included in the second transistor; the gate electrode included in the second transistor is electrically connected to one of a source electrode and a drain electrode which are included in the first transistor; and when j≥2, the jth sub memory cell is arranged over the j−1th sub memory cell.