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    Semiconductor element
    35.
    发明申请
    Semiconductor element 失效
    半导体元件

    公开(公告)号：US20060220026A1

    公开(公告)日：2006-10-05

    申请号：US10553628

    申请日：2004-11-24

    申请人： Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kenya Yamashita ,  Kunimasa Takahashi ,  Ryoko Miyanaga

    发明人： Masao Uchida ,  Makoto Kitabatake ,  Osamu Kusumoto ,  Kenya Yamashita ,  Kunimasa Takahashi ,  Ryoko Miyanaga

    IPC分类号： H01L31/0312

    CPC分类号： H01L29/7802 ,  H01L21/049 ,  H01L29/045 ,  H01L29/0696 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/41766 ,  H01L29/4238 ,  H01L29/518 ,  H01L29/66068 ,  H01L29/7838

    摘要： In a semiconductor device of the present invention, the top surface of an n-type silicon carbide layer formed on a silicon carbide substrate is miscut from the (0001) plane in the direction. A gate electrode, a source electrode and other elements are arranged such that in a channel region, the dominating current flows along a miscut direction. In the present invention, a gate insulating film is formed and then heat treatment is performed in an atmosphere containing a group-V element. In this way, the interface state density at the interface between the silicon carbide layer and the gate insulating film is reduced. As a result, the electron mobility becomes higher in a miscut direction A than in the direction perpendicular to the miscut direction A.

    摘要翻译： 在本发明的半导体器件中，形成在碳化硅衬底上的n型碳化硅层的顶表面从（0001）面向<11-20>方向错开。 栅电极，源电极等元件被布置成使得在通道区域中，主导电流沿着误差方向流动。 在本发明中，形成栅极绝缘膜，然后在含有V族元素的气氛中进行热处理。 以这种方式，碳化硅层和栅极绝缘膜之间的界面处的界面态密度降低。 结果，电子迁移率在错误方向A上比在与错误方向A垂直的方向上更高。

    Semiconductor device having an active region of alternating layers
    37.
    发明授权
    Semiconductor device having an active region of alternating layers 有权
    具有交替层的有源区的半导体器件

    公开(公告)号：US06690035B1

    公开(公告)日：2004-02-10

    申请号：US09980598

    申请日：2001-11-01

    申请人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Takeshi Uenoyama

    发明人： Toshiya Yokogawa ,  Kunimasa Takahashi ,  Osamu Kusumoto ,  Makoto Kitabatake ,  Takeshi Uenoyama

    IPC分类号： H01L310312

    CPC分类号： H01L29/155 ,  H01L29/045 ,  H01L29/1608 ,  H01L29/2003 ,  H01L29/365 ,  H01L29/812 ,  H01L29/872

    摘要： An active region 30 is formed on a substrate 3, which is made of SiC, GaN, or GaAs, for example, by alternately layering undoped layers 22 with a thickness of for example about 50 nm and n-type doped layers 23 with a thickness (for example, about 10 nm) that is thin enough that quantum effects can be achieved. Carriers spread out into the undoped layers 22 from sub-bands of the n-type doped layers 23 that occur due to quantum effects. In the undoped layers 22, which have a low concentration of impurities, the scattering of impurities is reduced, and therefore a high carrier mobility can be obtained there, and when the entire active region 30 has become depleted, a large withstand voltage value can be obtained due to the undoped layers 22 by taking advantage of the fact that there are no more carriers in the active region 30.

    摘要翻译： 有源区30形成在由SiC，GaN或GaAs制成的基板3上，例如通过交替层叠厚度例如约50nm的未掺杂层22和厚度为例如约50nm的n型掺杂层23 （例如，约10nm），其足够薄以使得能够实现量子效应。 由于量子效应，载体从n型掺杂层23的子带扩散到未掺杂层22中。 在具有低浓度杂质的未掺杂层22中，杂质的散射减少，因此可以获得高的载流子迁移率，并且当整个有源区30已经耗尽时，可以有大的耐受电压值 通过利用在有源区域30中不再具有载流子的事实，由于未掺杂层22而获得。

    Semiconductor device and method for fabricating the same
    40.
    发明授权
    Semiconductor device and method for fabricating the same 有权
    半导体装置及其制造方法

    公开(公告)号：US06580125B2

    公开(公告)日：2003-06-17

    申请号：US10204097

    申请日：2002-08-15

    申请人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

    发明人： Makoto Kitabatake ,  Toshiya Yokogawa ,  Osamu Kusumoto ,  Masao Uchida ,  Kunimasa Takahashi ,  Kenya Yamashita

    IPC分类号： H01L2976

    CPC分类号： H01L29/7395 ,  H01L29/1608 ,  H01L29/365 ,  H01L29/66068 ,  H01L29/7391 ,  H01L29/7828

    摘要： A DMOS device (or IGBT) includes an SiC substrate 2, an n-SiC layer 3 (drift region) formed in an epitaxial layer, a gate insulating film 6, a gate electrode 7a, a source electrode 7b formed to surround the gate electrode 7a, a drain electrode 7c formed on the lower surface of the SiC substrate 2, a p-SiC layer 4, an n+ SiC layer 3 formed to be present from under edges of the source electrode 7b to under associated edges of the gate electrode 7a. In addition, the device includes an n-type doped layer 10a containing a high concentration of nitrogen and an undoped layer 10b, which are stacked in a region in the surface portion of the epitaxial layer except the region where the n+ SiC layer 5 is formed. By utilizing a quantum effect, the device can have its on-resistance decreased, and can also have its breakdown voltage increased when in its off state.

    摘要翻译： DMOS器件（或IGBT）包括SiC衬底2，形成在外延层中的n-SiC层3（漂移区），栅极绝缘膜6，栅电极7a，形成为围绕栅电极的源电极7b 如图7a所示，形成在SiC衬底2的下表面上的漏极电极7c，形成为从源电极7b的下边缘形成的p-SiC层4，n + SiC层3到栅电极7a的相关边缘 。 此外，该器件包括含有高浓度氮的n型掺杂层10a和未掺杂层10b，层叠在除了形成n + SiC层5的区域之外的外延层的表面部分的区域中 。 通过利用量子效应，器件可以使其导通电阻降低，并且当其处于截止状态时也可以使其击穿电压增加。