公开(公告)号：US10461810B2

公开(公告)日：2019-10-29

申请号：US15638212

申请日：2017-06-29

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nathan Brooks ,  Swaminathan Sankaran ,  Bradley Allen Kramer ,  Mark W. Morgan ,  Baher Haroun

IPC: H04B5/00 ,  H01Q1/32 ,  H01Q1/38 ,  H04W4/80 ,  G06K7/10

Abstract: A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a near field communication (NFC) coupler located on the substrate. Each module has a housing that surrounds and encloses the substrate. The housing has a port region on a surface of the housing. Each module has a field confiner located between the NFC coupler and the port region on the housing configured to guide electromagnetic energy emanated from the NFC coupler through the port region to a port region of an adjacent module. A reflective surface is positioned adjacent the backside of each NFC coupler to reflect back side electromagnetic towards the port region.

公开(公告)号：US10371891B2

公开(公告)日：2019-08-06

申请号：US15800042

申请日：2017-10-31

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Daniel Lee Revier

IPC: G02B6/122 ,  H01L23/28 ,  H01P3/16 ,  H01P5/08 ,  H01P11/00 ,  H01Q1/22 ,  G02B6/12

Abstract: An encapsulated integrated circuit package is provided that includes an integrated circuit (IC) die. A radio frequency (RF) circuit on the IC die is operable to send and/or receive an RF signal having a selected frequency. Encapsulation material encapsulates the IC die. A photonic waveguide couples to the RF circuit and extends to an external surface of the encapsulated IC. The photonic waveguide may be formed by a photonic bandgap structure within the encapsulation material. A socket may be included with the encapsulated package that is coupled to an end of the photonic waveguide opposite the RF circuit.

公开(公告)号：US20190229051A1

公开(公告)日：2019-07-25

申请号：US16372455

申请日：2019-04-02

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/367 ,  H01L21/285 ,  H01L21/288 ,  H01L21/3205 ,  H01L23/48 ,  H01L23/31 ,  H01L23/522 ,  H01L23/532 ,  H01L21/324 ,  H01L21/3105 ,  H01L23/373

CPC classification number: H01L23/528 ,  H01L21/28556 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/31051 ,  H01L21/32051 ,  H01L21/32055 ,  H01L21/324 ,  H01L21/76802 ,  H01L21/76834 ,  H01L21/76876 ,  H01L21/76879 ,  H01L21/76885 ,  H01L21/76895 ,  H01L23/3107 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/481 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/53209 ,  H01L23/53276 ,  H01L2224/48463

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a graphitic via in the interconnect region. The graphitic via vertically connects a first interconnect in a first interconnect level to a second interconnect in a second, higher, interconnect level. The graphitic via includes a cohered nanoparticle film of nanoparticles in which adjacent nanoparticles cohere to each other, and a layer of graphitic material disposed on the cohered nanoparticle film. The nanoparticles include one or more metals suitable for catalysis of the graphitic material. The cohered nanoparticle film is formed by a method which includes an additive process. The graphitic via is electrically coupled to an active component of the integrated circuit.

公开(公告)号：US10121847B2

公开(公告)日：2018-11-06

申请号：US15462741

申请日：2017-03-17

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Barry Jon Male ,  Robert Alan Neidorff

IPC: H01L23/495 ,  H01L49/02 ,  H01L23/66

Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.

公开(公告)号：US20180269272A1

公开(公告)日：2018-09-20

申请号：US15462741

申请日：2017-03-17

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Barry Jon Male ,  Robert Alan Neidorff

IPC: H01L49/02 ,  H01L23/66 ,  H01L23/495

CPC classification number: H01L28/60 ,  H01L23/49575 ,  H01L23/66 ,  H01L2223/6611

Abstract: A galvanic isolation device includes a first integrated circuit (IC) die that has communication circuitry formed in a circuit layer below the top surface. A first conductive plate is formed on the IC die proximate the top surface, and is coupled to the communication circuitry. A dielectric isolation layer is formed over a portion of the top surface of the IC after the IC is fabricated such that the dielectric isolation layer completely covers the conductive plate. A second conductive plate is juxtaposed with the first conductive plate but separated by the dielectric isolation layer such that the first conductive plate and the second conductive plate form a capacitor. The second conductive plate is configured to be coupled to a second communication circuit.

公开(公告)号：US20180254230A1

公开(公告)日：2018-09-06

申请号：US15620361

申请日：2017-06-12

Applicant: Texas Instruments Incorporated

Inventor： Daniel Lee Revier ,  Benjamin Stassen Cook

IPC: H01L23/29 ,  G06F17/50 ,  H01L23/31 ,  H01L23/552 ,  H01L21/56 ,  H01L21/67

CPC classification number: H01L23/29 ,  G06F17/5068 ,  G06F2217/12 ,  G06F2217/40 ,  H01L21/56 ,  H01L21/67126 ,  H01L23/3114 ,  H01L23/552

Abstract: Methods and apparatus providing a graded package for a semiconductor are disclosed. An example apparatus includes a die; and a graded package encapsulating the die, the graded package including a material that is spatially varied from a first location of the graded package to a second location of the graded package.

公开(公告)号：US20180166369A1

公开(公告)日：2018-06-14

申请号：US15378236

申请日：2016-12-14

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Yong Lin

IPC: H01L23/495 ,  H01L23/00 ,  H01L21/48 ,  H01L23/29 ,  B32B15/092 ,  B32B7/10

Abstract: A device comprises a substrate) of a first material with a surface, which is modified by depositing a bi-layer nanoparticle film. The film includes a nanoparticle layer of a second material on top of and in contact with surface, and a nanoparticle layer of a third material on top of and in contact with the nanoparticle layer of the second material. The nanoparticles of the third material adhere to the nanoparticles of the second material. The substrate region adjoining surface comprises an admixture of the second material in the first material. A fourth material contacts and chemically/mechanically bonds to the nanoparticle layer of the third material.

公开(公告)号：US20180151471A1

公开(公告)日：2018-05-31

申请号：US15361399

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/373 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48

CPC classification number: H01L23/3677 ,  H01L21/4882 ,  H01L23/3731 ,  H01L23/3733 ,  H01L23/3736

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region includes a plurality of interconnect levels. Each interconnect level includes interconnects in dielectric material. The integrated circuit includes a thermal via in the interconnect region. The thermal via extends vertically in at least one of the interconnect levels in the interconnect region. The thermal via includes a cohered nanoparticle film in which adjacent nanoparticles are cohered to each other. The thermal via has a thermal conductivity higher than dielectric material touching the thermal via. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US09865527B1

公开(公告)日：2018-01-09

申请号：US15388616

申请日：2016-12-22

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Benjamin Stassen Cook ,  Yong Lin

IPC: H01L23/495 ,  H01L23/31 ,  H01L23/29 ,  H01L21/56 ,  H01L21/48

CPC classification number: H01L23/49558 ,  H01L21/4821 ,  H01L21/565 ,  H01L23/293 ,  H01L23/3121 ,  H01L23/49582

Abstract: A device comprises a substrate and an adhesive nanoparticle layer patterned into zones of electrical conductance and insulation on top of the substrate surface. A diffusion region adjoining the surface comprises an admixture of the nanoparticles in the substrate material. When the nanoparticle layer is patterned from originally all-conductive nanoparticles, the insulating zones are created by selective oxidation; when the nanoparticle layer is patterned from originally all-non-conductive nanoparticles, the conductive zones are created by depositing selectively a volatile reducing agent. A package of insulating material is in touch with the nanoparticle layer and fills any voids in the nanoparticle layer.

公开(公告)号：US20170350846A1

公开(公告)日：2017-12-07

申请号：US15173468

申请日：2016-06-03

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Mehmet Aslan

IPC: G01N27/22 ,  H01L21/02 ,  H01L21/288 ,  G01N31/22 ,  H01L49/02 ,  H01L21/321

Abstract: An integrated circuit (IC) with an impedance sensor fabricated on a surface of the substrate is disclosed. The impedance sensor includes a bottom conductive plate formed on the substrate. A sensing membrane is formed on the bottom conductive plate. A top conductive plate is formed on the sensing membrane, in which the top conductive plate is a fusion of conductive nanoparticles having a random three dimensional porosity that is permeable to a reagent.