公开(公告)号：US11424758B2

公开(公告)日：2022-08-23

申请号：US17307684

申请日：2021-05-04

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun Dusad ,  Chirag Chandrahas Shetty ,  Visvesvaraya Appala Pentakota

IPC: H03M1/50 ,  H03M1/14 ,  H03M1/20 ,  H03M1/44 ,  H03M1/36

Abstract: An analog-to-digital converter (ADC) having an input operable to receive an input voltage, VIN, and an output operable to output a digital code representative of VIN, the ADC including: a voltage-to-delay circuit having an input and an output, the input of the voltage-to-delay circuit coupled to the input of the ADC; a folding circuit having an input and an output, the input of the folding circuit coupled to the output of the voltage-to-delay circuit; and a time delay-based analog-to-digital converter backend having an input and a digital code output coupled to the output of the ADC, the input of the time delay-based analog-to-digital converter backend coupled to the output of the folding circuit.

公开(公告)号：US10075250B2

公开(公告)日：2018-09-11

申请号：US15395783

申请日：2016-12-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shagun Dusad ,  Nagarajan Viswanathan

IPC: H04B17/309 ,  H04L1/24 ,  H04L25/02 ,  H04B17/336

CPC classification number: H04B17/336 ,  H04B17/309 ,  H04L1/20 ,  H04L1/244 ,  H04L25/0202 ,  H04L25/0226

Abstract: A system includes a pseudorandom binary sequence (PRBS) generator configured to generate a first PRBS and a second PRBS and an exclusive-OR logic configured to exclusive-OR the first PRBS and the second PRBS to compute a third PRBS. The system also includes an adder, a correlator and a corrector. The adder adds the third PRBS to input data to compute summed data for transmission of the summed data across the channel. The correlator computes the exclusive-OR of the first PRBS and the second PRBS to reproduce the third PRBS and correlates output data from the channel to the reproduced third PRBS to compute a channel gain error and a channel memory error. The corrector extracts the input data from the output data from the channel using the computed channel gain and memory errors.

公开(公告)号：US09853657B2

公开(公告)日：2017-12-26

申请号：US15489124

申请日：2017-04-17

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Eeshan Miglani ,  Karthikeyan Gunasekaran ,  Santhosh Kumar Gowdhaman ,  Shagun Dusad

IPC: H03M3/00 ,  H03M1/06 ,  H03M1/00 ,  H03M1/74 ,  H03M7/30 ,  H03M1/12

CPC classification number: H03M3/50 ,  H03M1/00 ,  H03M1/001 ,  H03M1/0626 ,  H03M1/0665 ,  H03M1/12 ,  H03M1/747 ,  H03M3/30 ,  H03M3/34 ,  H03M3/422 ,  H03M3/458 ,  H03M7/3004

Abstract: The disclosure provides a delta sigma modulator that includes a first input port and a second input port. These ports receive a differential input signal. A DAC is coupled to the first input port and the second input port, and receives a differential feedback signal and a plurality of selection signals. A loop filter generates a differential filtered signal in response to a differential error signal. The differential error signal is proportional to a difference in the differential input signal and the differential feedback signal. A quantizer generates a quantized output signal in response to the differential filtered signal. A modified DWA block coupled between the quantizer and the DAC, generates the plurality of selection signals in response to a chop clock, a regular clock, the quantized output signal and a plurality of selection index signals. A selection index signal is dependent on previously generated plurality of selection signals.

公开(公告)号：US09806730B1

公开(公告)日：2017-10-31

申请号：US15395673

申请日：2016-12-30

Applicant: Texas Instruments Incorporated

Inventor： Shagun Dusad ,  Eeshan Miglani ,  Sandeep Jhanwar

IPC: H03M1/00 ,  H03M1/08 ,  H03M3/00

CPC classification number: H03M1/08 ,  H03M1/0682 ,  H03M1/66 ,  H03M3/464

Abstract: A current digital-to-analog converter (DAC) and an integrated circuit chip including the DAC are disclosed. The current DAC includes a switching circuit that includes a plurality of switches coupled to receive differential digital control signals and to provide first and second differential current outputs, a current source coupled to an upper rail and to a first node of the switching circuit, a first current sink coupled to a lower rail and to a second node of the switching circuit, and an interference cancellation circuit coupled to substantially prevent a tail capacitance current from flowing through the first and second differential current outputs.

公开(公告)号：US20170302287A1

公开(公告)日：2017-10-19

申请号：US15485552

申请日：2017-04-12

Applicant: Texas Instruments Incorporated

Inventor： Srinivas Kumar Reddy Naru ,  Visvesvaraya Pentakota Appala ,  Shagun Dusad ,  Neeraj Shrivastava ,  Viswanathan Nagarajan ,  Ani Xavier ,  Rishi Soundararajan ,  Sai Aditya Nurani ,  Roswald Francis

IPC: H03M1/06 ,  H03M1/12

CPC classification number: H03M1/06 ,  H03M1/1038 ,  H03M1/109 ,  H03M1/1205 ,  H03M1/164 ,  H03M1/361

Abstract: The disclosure provides an analog to digital converter (ADC). The ADC includes a flash ADC. The flash ADC generates a flash output in response to an input signal, and an error correction block generates a known pattern. A selector block is coupled to the flash ADC and the error correction block, and generates a plurality of selected signals in response to the flash output and the known pattern. A digital to analog converter (DAC) is coupled to the selector block, and generates a coarse analog signal in response to the plurality of selected signals. A residue amplifier is coupled to the DAC, and generates a residual analog signal in response to the coarse analog signal, the input signal and an analog PRBS (pseudo random binary sequence) signal. A residual ADC generates a residual code in response to the residual analog signal.

公开(公告)号：US09722622B2

公开(公告)日：2017-08-01

申请号：US15136368

申请日：2016-04-22

Applicant: Texas Instruments Incorporated

Inventor： Gehesh Edakkuttathil Muhammed ,  Naveen KV ,  Arun Mohan ,  Shagun Dusad

IPC: H03M1/12 ,  H01L23/522 ,  H01L27/08 ,  H01G4/30 ,  H03M1/80 ,  H01G4/38 ,  H01L49/02

CPC classification number: H03M1/12 ,  H01G4/30 ,  H01G4/38 ,  H01G4/385 ,  H01L23/5223 ,  H01L27/0805 ,  H01L28/90 ,  H03M1/804

Abstract: The disclosure provides a capacitor array. The capacitor array includes one or more first metal plates vertically stacked parallel to each other. A second metal plate is horizontally stacked to couple one end of each first metal plate of the one or more first metal plates. One or more third metal plates are vertically stacked parallel to the one or more first metal plates. Each third metal plate of the one or more third metal plates is stacked between two first metal plates.

公开(公告)号：US09548752B1

公开(公告)日：2017-01-17

申请号：US15048027

申请日：2016-02-19

Applicant: Texas Instruments Incorporated

Inventor： Neeraj Shrivastava ,  Supreet Joshi ,  Himanshu Varshney ,  Jafar Sadique Kaviladath ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: H03M1/66 ,  H03M1/10 ,  H03M1/78 ,  H03M1/74

CPC classification number: H03M1/1009 ,  H03M1/1019 ,  H03M1/1057 ,  H03M1/66 ,  H03M1/742 ,  H03M1/745 ,  H03M1/785

Abstract: The disclosure provides a current steering digital to analog converter (DAC) that includes a plurality of DAC elements. At least one DAC element of the plurality of DAC elements is coupled to a calibration circuit. The calibration circuit includes a fixed current source coupled to a primary node of the DAC element through a first estimation switch. A digital code generator is coupled to the primary node, and generates a first digital code corresponding to a primary voltage generated at the primary node. The digital code generator generates a second digital code. A correction DAC is coupled to the digital code generator and generates a bias voltage based on the second digital code. The bias voltage is provided to the DAC element such that a current flowing through each DAC element of the plurality of DAC elements is equal.

Abstract translation: 本公开提供了包括多个DAC元件的电流转向数模转换器（DAC）。 多个DAC元件中的至少一个DAC元件耦合到校准电路。 校准电路包括通过第一估计开关耦合到DAC元件的主节点的固定电流源。 数字码发生器耦合到主节点，并且产生对应于在主节点处产生的主电压的第一数字码。 数字代码生成器产生第二数字代码。 校正DAC耦合到数字代码发生器并且基于第二数字代码产生偏置电压。 偏置电压被提供给DAC元件，使得流过多个DAC元件中的每个DAC元件的电流相等。

公开(公告)号：US09013226B2

公开(公告)日：2015-04-21

申请号：US13627396

申请日：2012-09-26

Applicant: Texas Instruments Incorporated

Inventor： Shagun Dusad ,  Visvesvaraya Pentakota

IPC: H03K17/16

CPC classification number: H03K17/16 ,  H03F1/32 ,  H03F3/45179 ,  H03F2203/45394 ,  H03F2203/45684 ,  H03F2203/45702 ,  H03K17/165

Abstract: Various embodiments of circuits configured to improve second order harmonic distortion of Metal Oxide Semiconductor (MOS) transistors operating in linear region are provided. In one embodiment, a circuit includes an averaging circuit configured to average signals at a drain and a source of a MOS transistor and provide the averaged signal to a gate of the MOS transistor, and one or more current sources coupled with the gate; the circuit is configured to vary voltage at the gate so as to vary a resistance of the MOS transistor. The averaging circuit comprises a first MOS circuit coupled between the drain and the gate, a first capacitor coupled in parallel to the first MOS circuit between the drain and the gate, a second MOS circuit coupled between the source and the gate, and a second capacitor coupled in parallel to the second MOS circuit between the source and the gate.

Abstract translation: 提供了构造成改善以线性区域工作的金属氧化物半导体（MOS）晶体管的二阶谐波失真的电路的各种实施例。 在一个实施例中，电路包括平均电路，其被配置为平均MOS晶体管的漏极和源极处的信号，并将平均信号提供给MOS晶体管的栅极以及与栅极耦合的一个或多个电流源; 电路被配置为改变栅极处的电压，以便改变MOS晶体管的电阻。 平均电路包括耦合在漏极和栅极之间的第一MOS电路，与漏极和栅极之间的第一MOS电路并联耦合的第一电容器，耦合在源极和栅极之间的第二MOS电路和第二电容器 在源极和栅极之间并联耦合到第二MOS电路。

公开(公告)号：US20150077070A1

公开(公告)日：2015-03-19

申请号：US14446815

申请日：2014-07-30

Applicant: TEXAS INSTRUMENTS INCORPORATED

Inventor： Shuaeb Fazeel ,  Eeshan Miglani ,  Visvesvaraya Pentakota ,  Shagun Dusad

IPC: G05F1/575

CPC classification number: G05F1/575 ,  G05F1/467 ,  G05F3/222 ,  G05F3/242

Abstract: A voltage regulator that provides feedforward cancellation of power supply noise is disclosed. The voltage regulator includes a process tracking circuit that receives a supply voltage and generates a proportional voltage. A tracking capacitor is coupled to the process tracking circuit and generates an injection voltage based on the proportional voltage. An Ahuja compensated regulator generates a regulated voltage. The injection voltage is provided on a feedback path of the Ahuja compensated regulator.

Abstract translation: 公开了一种提供电源噪声前馈消除的电压调节器。 电压调节器包括接收电源电压并产生比例电压的过程跟踪电路。 跟踪电容器耦合到过程跟踪电路，并基于比例电压产生注入电压。 Ahuja补偿稳压器产生调节电压。 在Ahuja补偿调节器的反馈路径上提供注入电压。

公开(公告)号：US20250105854A1

公开(公告)日：2025-03-27

申请号：US18973169

申请日：2024-12-09

Applicant: Texas Instruments Incorporated

Inventor： Visvesvaraya Appala Pentakota ,  Srinivas Kumar Reddy Naru ,  Chirag Shetty ,  Eeshan Miglani ,  Neeraj Shrivastava ,  Narasimhan Rajagopal ,  Shagun Dusad

IPC: H03M1/10

Abstract: In described examples, a circuit includes a multiplexer. The multiplexer receives an input voltage and a calibration signal. An analog-to-digital converter (ADC) is coupled to the multiplexer and generates an output code in response to the calibration signal. A storage circuit is coupled to the ADC and stores the input code representative of the calibration signal at an address corresponding to the output code. The stored input code includes an index value and a coarse value.