公开(公告)号：US20230386906A1

公开(公告)日：2023-11-30

申请号：US18446521

申请日：2023-08-09

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Ting-Chen Tseng ,  Sih-Hao Liao ,  Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L21/22 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L23/48

CPC classification number: H01L21/76822 ,  H01L21/22 ,  H01L21/76838 ,  H01L23/49822 ,  H01L23/49827 ,  H01L21/31144 ,  H01L23/49833 ,  H01L21/4857 ,  H01L23/481 ,  H01L23/49816 ,  H01L23/5389

Abstract: In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.

公开(公告)号：US20230253338A1

公开(公告)日：2023-08-10

申请号：US18302461

申请日：2023-04-18

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/538 ,  H01L25/16 ,  H01L21/56 ,  H01L21/768 ,  H01L21/288 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L23/31 ,  H01L21/683 ,  H01L25/00

CPC classification number: H01L23/5389 ,  H01L23/5384 ,  H01L23/5386 ,  H01L25/16 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76873 ,  H01L21/76879 ,  H01L21/2885 ,  H01L21/76834 ,  H01L24/24 ,  H01L24/19 ,  H01L25/105 ,  H01L21/4857 ,  H01L21/486 ,  H01L23/3128 ,  H01L21/568 ,  H01L21/6835 ,  H01L25/50 ,  H01L25/0657

Abstract: In an embodiment, a device includes: a molding compound; an integrated circuit die encapsulated in the molding compound; a through via adjacent the integrated circuit die; and a redistribution structure over the integrated circuit die, the molding compound, and the through via, the redistribution structure electrically connected to the integrated circuit die and the through via, the redistribution structure including: a first dielectric layer disposed over the molding compound; a first conductive via extending through the first dielectric layer; a second dielectric layer disposed over the first dielectric layer and the first conductive via; and a second conductive via extending through the second dielectric layer and into a portion of the first conductive via, an interface between the first conductive via and the second conductive via being non-planar.

公开(公告)号：US11164839B2

公开(公告)日：2021-11-02

申请号：US16413591

申请日：2019-05-15

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Po-Han Wang ,  Yung-Chi Chu ,  Hung-Chun Cho

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498 ,  H01L23/538 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01L25/065 ,  H01L21/683 ,  C09J165/00

Abstract: A package structure includes a semiconductor die and a redistribution circuit structure. The redistribution circuit structure is disposed on and electrically connected to the semiconductor die and includes a patterned conductive layer, a dielectric layer, and an inter-layer film. The dielectric layer is disposed on the patterned conductive layer. The inter-layer film is sandwiched between the dielectric layer and the patterned conductive layer, and the patterned conductive layer is separated from the dielectric layer through the inter-layer film.

公开(公告)号：US20210313292A1

公开(公告)日：2021-10-07

申请号：US16836934

申请日：2020-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Shih-Peng Tai ,  Yu-Hsiang Hu ,  I-Chia Chen

IPC: H01L23/00

Abstract: A semiconductor package including a plurality of semiconductor devices, an insulating layer, and a redistribution layer is provided. The insulating layer is disposed over the semiconductor device. The redistribution layer is disposed over the insulating layer and electrically connected to the semiconductor device. The redistribution layer includes a conductive line portion. The semiconductor package has a stitching zone, and the insulating layer has a ridge structure on a surface away from the semiconductor device and positioned within the stitching zone.

公开(公告)号：US11101176B2

公开(公告)日：2021-08-24

申请号：US16415437

申请日：2019-05-17

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Yu-Hsiang Hu ,  Hung-Jui Kuo

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532 ,  H01L23/31 ,  H01L21/56

Abstract: A method of fabricating a redistribution circuit structure including the following steps is provided. A conductive via is formed. A photosensitive dielectric layer is formed to cover the conductive via. The photosensitive dielectric layer is partially removed to reveal the conductive via at least through an exposure and development process. A redistribution wiring is formed on the photosensitive dielectric layer and the revealed conductive via.

公开(公告)号：US20210125886A1

公开(公告)日：2021-04-29

申请号：US16667854

申请日：2019-10-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao

IPC: H01L23/31 ,  H01L23/498 ,  H01L25/16

Abstract: A semiconductor package including a semiconductor die, an encapsulant, an electrical connector, a conductive pad and an inter-dielectric layer is provided. The encapsulant encapsulates the semiconductor die. The electrical connector is disposed over the semiconductor die. The conductive pad contacts the electrical connector and is disposed between the semiconductor die and the electrical connector. The inter-dielectric layer is disposed over the semiconductor die, wherein the inter-dielectric layer comprises an opening, and a portion of the opening is occupied by the conductive pad and the electrical connector.

公开(公告)号：US20190333782A1

公开(公告)日：2019-10-31

申请号：US15964092

申请日：2018-04-27

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L21/56 ,  H01L23/31 ,  H01L23/367 ,  H01L23/04 ,  H01L23/498 ,  H01L21/48 ,  H01L25/065 ,  H01L25/00

Abstract: A semiconductor package manufacturing method thereof are provided. The semiconductor package includes a high-power device die, a redistribution structure, a heat dissipation module and a molding compound. The high-power device die has a front side and a back side opposite to the front side. The redistribution structure is disposed at the front side. The heat dissipation module is in direct contact with the back side. The molding compound is disposed between the redistribution structure and the heat dissipation module, and surrounding the high-power device die. The molding compound has a body portion and an extended portion. An interface between the body portion and the heat dissipation module is substantially parallel to the back side of the high-power device die. A thickness of the extended portion is greater than a thickness of the body portion.

公开(公告)号：US10332856B2

公开(公告)日：2019-06-25

申请号：US15806347

申请日：2017-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Po-Han Wang

IPC: H01L25/11 ,  H01L23/00 ,  H01L25/04 ,  H01L25/07 ,  H01L25/075 ,  H01L25/065

Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

公开(公告)号：US20190139924A1

公开(公告)日：2019-05-09

申请号：US15806347

申请日：2017-11-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Wei-Chih Chen ,  Hung-Jui Kuo ,  Yu-Hsiang Hu ,  Sih-Hao Liao ,  Po-Han Wang

IPC: H01L23/00

CPC classification number: H01L24/24 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/25 ,  H01L24/73 ,  H01L24/82 ,  H01L25/042 ,  H01L25/0655 ,  H01L25/072 ,  H01L25/0753 ,  H01L25/115 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/214 ,  H01L2224/2402 ,  H01L2224/24101 ,  H01L2224/24137 ,  H01L2224/2499 ,  H01L2224/25171 ,  H01L2224/32225 ,  H01L2224/73209 ,  H01L2224/73267 ,  H01L2224/82007 ,  H01L2224/82106 ,  H01L2224/92244

Abstract: A package structure including at least one semiconductor die, an insulating encapsulant, an insulating layer, conductive pillars, a dummy pillar, a first seed layer and a redistribution layer is provided. The semiconductor die have a first surface and a second surface opposite to the first surface. The insulating encapsulant is encapsulating the semiconductor die. The insulating layer is disposed on the first surface of the semiconductor die and on the insulating encapsulant. The conductive pillars are located on the semiconductor die. The dummy pillar is located on the insulating encapsulant. The first seed layer is embedded in the insulating layer, wherein the first seed layer is located in between the conductive pillars and the semiconductor die, and located in between the dummy pillar and the insulating encapsulant. The redistribution layer is disposed over the insulating layer and is electrically connected to the semiconductor die through the conductive pillars.

公开(公告)号：US20190139847A1

公开(公告)日：2019-05-09

申请号：US15846232

申请日：2017-12-19

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Po-Han Wang ,  Hung-Jui Kuo ,  Yu-Hsiang Hu

IPC: H01L23/31 ,  H01L23/00 ,  H01L21/56 ,  H01L21/3105

Abstract: A package structure and a method of manufacturing the same are provided. The package structure includes a die, a first encapsulant, a second encapsulant, a protection layer, a RDL structure and a connector. The first encapsulant is aside a first sidewall of the die, at least encapsulating a portion of the first sidewall of the die. The second encapsulant is aside a second sidewall of the die, encapsulating the second sidewall of the die. The protection layer is aside the first sidewall of the die and on the first encapsulant. The RDL structure is on a first surface of the die. The connector is electrically connected to the die through the RDL structure.