公开(公告)号：US20200312894A1

公开(公告)日：2020-10-01

申请号：US16900985

申请日：2020-06-14

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chao-Ching Chang ,  Sheng-Chan Li ,  Chih-Hui Huang ,  Jian-Shin Tsai ,  Cheng-Yi Wu ,  Chia-Hsing Chou ,  Yi-Ming Lin ,  Min-Hui Lin ,  Chin-Szu Lee

IPC: H01L27/146 ,  H01L21/762 ,  H01L21/02

Abstract: A plurality of radiation-sensing doped regions are formed in a substrate. A trench is formed in the substrate between the radiation-sensing doped regions. A SiOCN layer is filled in the trench by reacting Bis(tertiary-butylamino)silane (BTBAS) and a gas mixture comprising N2O, N2 and O2 through a plasma enhanced atomic layer deposition (PEALD) method, to form an isolation structure between the radiation-sensing doped regions.

公开(公告)号：US10734285B2

公开(公告)日：2020-08-04

申请号：US16178819

申请日：2018-11-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Chih-Hui Huang ,  Kuo-Ming Wu

IPC: H01L21/822 ,  H01L23/532 ,  H01L23/528 ,  H01L23/522 ,  H01L21/768 ,  H01L23/00 ,  H01L25/065

Abstract: In some embodiments, a method for bonding semiconductor wafers is provided. The method includes forming a first integrated circuit (IC) over a central region of a first semiconductor wafer. A first ring-shaped bonding support structure is formed over a ring-shaped peripheral region of the first semiconductor wafer, where the ring-shaped peripheral region of the first semiconductor wafer encircles the central region of the first semiconductor wafer. A second semiconductor wafer is bonded to the first semiconductor wafer, such that a second IC arranged on the second semiconductor wafer is electrically coupled to the first IC.

公开(公告)号：US10475847B2

公开(公告)日：2019-11-12

申请号：US15231390

申请日：2016-08-08

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Lu ,  Chih-Hui Huang ,  Sheng-Chan Li ,  Jung-Chih Tsao ,  Yao-Hsiang Liang

IPC: H01L21/285 ,  H01L21/3205 ,  H01L21/3213 ,  H01L27/146

Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.

公开(公告)号：US10062720B2

公开(公告)日：2018-08-28

申请号：US15635673

申请日：2017-06-28

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Yen-Ting Chiang ,  Ching-Chun Wang ,  Dun-Nian Yaung ,  Hsiao-Hui Tseng ,  Chih-Hui Huang ,  Shyh-Fann Ting ,  Shih Pei Chou ,  Sheng-Chan Li

IPC: H01L29/76 ,  H01L27/146

CPC classification number: H01L27/1463 ,  H01L27/14621 ,  H01L27/14627 ,  H01L27/14636 ,  H01L27/1464 ,  H01L27/14685 ,  H01L27/14689

Abstract: The present disclosure relates to an integrated circuit, and an associated method of formation. In some embodiments, the integrated circuit comprises a deep trench grid disposed at a back side of a substrate. A passivation layer lines the deep trench grid within the substrate. The passivation layer includes a first high-k dielectric layer and a second high-k dielectric layer disposed over the first high-k dielectric layer. A first dielectric layer is disposed over the passivation layer, lining the deep trench grid and extending over an upper surface of the substrate. A second dielectric layer is disposed over the first dielectric layer and enclosing remaining spaces of the deep trench grid to form air-gaps at lower portions of the deep trench grid. The air-gaps are sealed by the first dielectric layer or the second dielectric layer below the upper surface of the substrate.

公开(公告)号：US12272715B2

公开(公告)日：2025-04-08

申请号：US17353003

申请日：2021-06-21

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Hau-Yi Hsiao ,  Che Wei Yang ,  Sheng-Chau Chen ,  Cheng-Yuan Tsai

IPC: H01L27/146 ,  H01L21/768

Abstract: Various embodiments of the present disclosure are directed towards an image sensor having a semiconductor substrate comprising a front-side surface opposite a back-side surface. A plurality of photodetectors is disposed in the semiconductor substrate. An isolation structure extends into the back-side surface of the semiconductor substrate and is disposed between adjacent photodetectors. The isolation structure includes a metal core, a conductive liner disposed between the semiconductor substrate and the metal core, and a first dielectric liner disposed between the conductive liner and the semiconductor substrate. The metal core comprises a first metal material and the conductive liner comprises the first metal material and a second metal material different from the first metal material.

公开(公告)号：US12176370B2

公开(公告)日：2024-12-24

申请号：US17336852

申请日：2021-06-02

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Min-Feng Kao ,  Dun-Nian Yaung ,  Jen-Cheng Liu ,  Wen-Chang Kuo ,  Sheng-Chau Chen ,  Feng-Chi Hung ,  Sheng-Chan Li

IPC: H01L27/146

Abstract: Some embodiments relate to an image sensor. The image sensor includes a semiconductor substrate including a pixel region and a peripheral region. A backside isolation structure extends into a backside of the semiconductor substrate and laterally surrounds the pixel region. The backside isolation structure includes a metal core, and a dielectric liner separates the metal core from the semiconductor substrate. A conductive feature is disposed over a front side of the semiconductor substrate. A through substrate via extends from the backside of the semiconductor substrate through the peripheral region to contact the conductive feature. The through substrate via is laterally offset from the backside isolation structure. A conductive bridge is disposed beneath the backside of the semiconductor substrate and electrically couples the metal core of the backside isolation structure to the through substrate via.

公开(公告)号：US12142628B2

公开(公告)日：2024-11-12

申请号：US17859834

申请日：2022-07-07

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Chi-Ming Lu ,  Chih-Hui Huang ,  Sheng-Chan Li ,  Jung-Chih Tsao ,  Yao-Hsiang Liang

IPC: H01L21/3213 ,  H01L21/285 ,  H01L21/3205 ,  H01L27/146

Abstract: A method of fabricating a semiconductor device includes forming a first film having a first film stress type and a first film stress intensity over a substrate and forming a second film having a second film stress type and a second film stress intensity over the first film. The second film stress type is different than the first film stress type. The second film stress intensity is about same as the first film stress intensity. The second film compensates stress induced effect of non-flatness of the substrate by the first film.

公开(公告)号：US11749760B2

公开(公告)日：2023-09-05

申请号：US17744398

申请日：2022-05-13

Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.

Inventor： Cheng-Han Lin ,  Chao-Ching Chang ,  Yi-Ming Lin ,  Yen-Ting Chou ,  Yen-Chang Chen ,  Sheng-Chan Li ,  Cheng-Hsien Chou

IPC: H01L31/0216 ,  H01L31/18 ,  H01L27/146 ,  H01L31/0232

CPC classification number: H01L31/0216 ,  H01L27/14636 ,  H01L31/0232 ,  H01L31/18

Abstract: A device and method for fabricating the same is disclosed. For example, the device includes a sensor having a front side and a back side, a metal interconnect layer formed on the front side of the sensor, an anti-reflective coating formed on the back side of the sensor, a composite etch stop mask layer formed on the anti-reflective coating wherein the composite etch stop mask layer includes a hydrogen rich layer and a compressive high density layer, and a light filter formed on the composite etch stop mask layer.

公开(公告)号：US11735624B2

公开(公告)日：2023-08-22

申请号：US17361723

申请日：2021-06-29

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Alexander Kalnitsky ,  Ru-Liang Lee ,  Ming Chyi Liu ,  Sheng-Chan Li ,  Sheng-Chau Chen

IPC: H01L27/146 ,  H01L49/02 ,  H01L23/522 ,  H01L21/768

CPC classification number: H01L28/87 ,  H01L21/768 ,  H01L23/5223 ,  H01L28/90 ,  H01L27/14603

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a dielectric stack disposed over a substrate. The dielectric stack has a first plurality of layers interleaved between a second plurality of layers. The dielectric stack has one or more surfaces that define a plurality of indentations recessed into a side of the dielectric stack at different vertical heights corresponding to the second plurality of layers. A capacitor structure lines the one or more surfaces of the dielectric stack. The capacitor structure includes conductive electrodes separated by a capacitor dielectric.

公开(公告)号：US11705470B2

公开(公告)日：2023-07-18

申请号：US17219960

申请日：2021-04-01

Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.

Inventor： Sheng-Chan Li ,  Cheng-Hsien Chou ,  Cheng-Yuan Tsai ,  Keng-Yu Chou ,  Yeur-Luen Tu

IPC: H01L27/146

CPC classification number: H01L27/14629 ,  H01L27/14607

Abstract: The present disclosure, in some embodiments, relates to an integrated chip. The integrated chip includes a photodetector arranged within a substrate. The substrate has surfaces defining one or more protrusions arranged along a first side of the substrate over the photodetector. One or more isolation structures are arranged within one or more trenches defined by sidewalls of the substrate arranged on opposing sides of the photodetector. The one or more trenches extend from the first side of the substrate to within the substrate. The one or more isolation structures respectively include a reflective medium configured to reflect electromagnetic radiation.