公开(公告)号：US11557654B2

公开(公告)日：2023-01-17

申请号：US17511586

申请日：2021-10-27

Applicant: United Microelectronics Corp.

Inventor： Chia-Jung Hsu ,  Chin-Hung Chen ,  Chun-Ya Chiu ,  Chih-Kai Hsu ,  Ssu-I Fu ,  Tsai-Yu Wen ,  Shi You Liu ,  Yu-Hsiang Lin

IPC: H01L29/10 ,  H01L21/265 ,  H01L29/167 ,  H01L29/06

Abstract: A method for fabricating of semiconductor device is provided, including providing a substrate. A first trench isolation and a second trench isolation are formed in the substrate. A portion of the substrate is etched to have a height between a top and a bottom of the first and second trench isolations. A germanium (Ge) doped layer region is formed in the portion of the substrate. A fluorine (F) doped layer region is formed in the portion of the substrate, lower than and overlapping with the germanium doped layer region. An oxidation process is performed on the portion of the substrate to form a gate oxide layer between the first and second trench isolations.

公开(公告)号：US10651275B2

公开(公告)日：2020-05-12

申请号：US15893681

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66 ,  H01L21/324 ,  H01L21/265 ,  H01L21/8234

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US20190214465A1

公开(公告)日：2019-07-11

申请号：US15893681

申请日：2018-02-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shi-You Liu ,  Tsai-Yu Wen ,  Ching-I Li ,  Ya-Yin Hsiao ,  Chih-Chiang Wu ,  Yu-Chun Liu ,  Ti-Bin Chen ,  Shao-Ping Chen ,  Huan-Chi Ma ,  Chien-Wen Yu

IPC: H01L29/10 ,  H01L29/78 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66

Abstract: A method for fabricating p-type field effect transistor (FET) includes the steps of first providing a substrate, forming a pad layer on the substrate, forming a well in the substrate, performing an ion implantation process to implant germanium ions into the substrate to form a channel region, and then conducting an anneal process to divide the channel region into a top portion and a bottom portion. After removing the pad layer, a gate structure is formed on the substrate and a lightly doped drain (LDD) is formed adjacent to two sides of the gate structure.

公开(公告)号：US09859164B1

公开(公告)日：2018-01-02

申请号：US15294792

申请日：2016-10-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ming-Shiou Hsieh ,  Chun-Yao Yang ,  Shi-You Liu ,  Rong-Sin Lin ,  Han-Ting Yen ,  Neng-Hui Yang ,  Tsai-Yu Wen ,  Ching-I Li

IPC: H01L21/8234 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02

CPC classification number: H01L21/823431 ,  H01L21/02115 ,  H01L21/02271 ,  H01L21/265 ,  H01L21/324 ,  H01L21/823468 ,  H01L21/823481

Abstract: A method for manufacturing fins includes following steps. A substrate including a plurality of fins formed thereon is provided. At least an ion implantation is performed to the fins. A thermal process is performed after the ion implantation. An insulating layer is formed on the substrate, and the fins are embedded in the insulating layer. Thereafter, a portion of the insulating layer is removed to form an isolation structure on the substrate, and the fins are exposed from a top surface of the isolation structure. The insulating layer is formed after the ion implantation and the thermal process. Or, the isolation structure is formed before the ion implantation, or between the ion implantation and the thermal process.

公开(公告)号：US20170358684A1

公开(公告)日：2017-12-14

申请号：US15206319

申请日：2016-07-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Cheng Chen ,  Tsai-Yu Wen ,  Shan Ye ,  Tsuo-Wen Lu

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/49 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L21/28291 ,  H01L29/4966 ,  H01L29/516 ,  H01L29/517 ,  H01L29/6684

Abstract: A semiconductor device includes a substrate, an electrode layer disposed on the substrate, and a tri-layered gate-control stack sandwiched between the substrate and the electrode layer. The tri-layered gate-control stack includes a ferroelectric layer disposed on the substrate, a mid-gap metal layer sandwiched between the ferroelectric layer and the substrate, and an anti-ferroelectric layer. The anti-ferroelectric layer is sandwiched between the substrate and the mid-gap metal layer. Alternatively, the ferroelectric layer and the mid-gap metal layer are sandwiched between the anti-ferroelectric layer and the substrate.

公开(公告)号：US09653549B2

公开(公告)日：2017-05-16

申请号：US15166271

申请日：2016-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chun Jen Chen ,  Bin-Siang Tsai ,  Tsai-Yu Wen ,  Yu Shu Lin ,  Chin-Sheng Yang

IPC: H01L29/66 ,  H01L29/06 ,  H01L21/02 ,  H01L29/423 ,  H01L29/78 ,  H01L29/165 ,  H01L29/775 ,  H01L29/41

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02587 ,  H01L21/02603 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/76224 ,  H01L29/0673 ,  H01L29/068 ,  H01L29/16 ,  H01L29/165 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L2029/7858

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate; a first nanowire disposed over the substrate; a second nanowire disposed over the substrate; a first pad formed at first ends of the first and second nanowires, a second pad formed at second ends of the first and second nanowires, wherein the pads comprise different materials than the nanowires; and a gate surrounding at least a portion of each of the first and second nanowires.

公开(公告)号：US20160329400A1

公开(公告)日：2016-11-10

申请号：US15215609

申请日：2016-07-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Tsai-Yu Wen ,  Chin-Sheng Yang ,  Chun-Jen Chen ,  Tsuo-Wen Lu ,  Yu-Ren Wang

IPC: H01L29/06 ,  H01L29/161 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/0673 ,  H01L21/02164 ,  H01L21/02233 ,  H01L21/02236 ,  H01L21/02381 ,  H01L21/0243 ,  H01L21/0245 ,  H01L21/02452 ,  H01L21/02532 ,  H01L21/02535 ,  H01L21/02603 ,  H01L21/02612 ,  H01L21/02639 ,  H01L21/02664 ,  H01L21/30604 ,  H01L21/31658 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66439 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.

Abstract translation: 形成纳米线的方法包括提供基底。 蚀刻衬底以形成至少一个鳍。 随后，在鳍的上部形成第一外延层。 之后，在翅片的中间部分形成底切。 形成第二外延层以填充底切。 最后，将鳍状物，第一外延层和第二外延层氧化以将第一外延层和第二外延层冷凝成含锗纳米线。

公开(公告)号：US09117878B2

公开(公告)日：2015-08-25

申请号：US13710483

申请日：2012-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Keng-Jen Lin ,  Yu-Ren Wang ,  Chih-Chung Chen ,  Tsuo-Wen Lu ,  Tsai-Yu Wen

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/02 ,  H01L21/321

CPC classification number: H01L21/76232 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/32105

Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.

Abstract translation: 一种制造半导体结构的方法包括以下步骤。 首先，提供半导体衬底，并且在半导体衬底上形成图案化衬垫层以露出半导体衬底的一部分。 然后，从图案化衬垫层露出的半导体衬底被蚀刻掉以在半导体衬底内部形成沟槽。 在沟槽的表面上选择性地形成选择性生长的材料层，然后将电介质前体材料填充到沟槽中。 最后，进行转换处理以将电介质前体材料同时转变为电介质材料，并将选择性生长的材料层转变成含氧非晶材料层。

公开(公告)号：US20140162431A1

公开(公告)日：2014-06-12

申请号：US13710483

申请日：2012-12-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Keng-Jen Lin ,  Yu-Ren Wang ,  Chih-Chung Chen ,  Tsuo-Wen Lu ,  Tsai-Yu Wen

IPC: H01L21/762

CPC classification number: H01L21/76232 ,  H01L21/02164 ,  H01L21/02219 ,  H01L21/02282 ,  H01L21/02304 ,  H01L21/02326 ,  H01L21/02337 ,  H01L21/32105

Abstract: A method for manufacturing a semiconductor structure includes the following steps. First, a semiconductor substrate is provided and a patterned pad layer is formed on the semiconductor substrate so as to expose a portion of the semiconductor substrate. Then, the semiconductor substrate exposed from the patterned pad layer is etched away to form a trench inside the semiconductor substrate. A selectively-grown material layer is selectively formed on the surface of the trench, followed by filling a dielectric precursor material into the trench. Finally, a transformation process is carried out to concurrently transform the dielectric precursor material into a dielectric material and transform the selectively-grown material layer into an oxygen-containing amorphous material layer.

Abstract translation: 一种制造半导体结构的方法包括以下步骤。 首先，提供半导体衬底，并且在半导体衬底上形成图案化衬垫层以露出半导体衬底的一部分。 然后，从图案化衬垫层露出的半导体衬底被蚀刻掉以在半导体衬底内部形成沟槽。 在沟槽的表面上选择性地形成选择性生长的材料层，然后将电介质前体材料填充到沟槽中。 最后，进行转换处理以将电介质前体材料同时转变为电介质材料，并将选择性生长的材料层转变成含氧非晶材料层。