公开(公告)号：US20190131302A1

公开(公告)日：2019-05-02

申请号：US15802450

申请日：2017-11-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Che-Jung Hsu ,  Yu-Cheng Tung ,  JIANJUN YANG ,  Yuan-Hsiang Chang ,  Chih-Chien Chang ,  WEICHANG LIU ,  Shen-De Wang ,  KOK WUN TAN

IPC: H01L27/092 ,  H01L27/11573 ,  H01L29/66 ,  H01L29/78 ,  H01L29/792

CPC classification number: H01L27/0924 ,  H01L27/11573 ,  H01L29/66795 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/792

Abstract: A method of manufacturing FinFET semiconductor devices in memory regions and logic regions includes the steps of forming a first gate material layer on a substrate and fins, patterning the first gate material layer to form a control gate, forming a second gate material layer on the substrate and fins, performing an etch process to the cell region so that the second gate material layer in the cell region is lower than the second gate material layer in the peripheral region, patterning the second gate material layer to form a select gate in the cell region and a dummy gate in the logic region respectively.

公开(公告)号：US10090465B2

公开(公告)日：2018-10-02

申请号：US15359975

申请日：2016-11-23

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Liang Yi ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00

Abstract: A semiconductor device is provided, including a lower conducting layer formed above a substrate, an upper conducting layer, and a memory cell structure formed on the lower conducting layer (such as formed between the lower and upper conducting layers). The memory cell structure includes a bottom electrode formed on the lower conducting layer and electrically connected to the lower conducting layer, a transitional metal oxide (TMO) layer formed on the bottom electrode, a TMO sidewall oxides formed at sidewalls of the TMO layer, a top electrode formed on the TMO layer, and spacers formed on the bottom electrode. The upper conducting layer is formed on the top electrode and electrically connected to the top electrode.

公开(公告)号：US20180205013A1

公开(公告)日：2018-07-19

申请号：US15441261

申请日：2017-02-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Chia-Ching Hsu ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L27/2436 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/146 ,  H01L45/1683

Abstract: A method of forming a Resistive Random Access Memory (RRAM) includes the following steps. A first dielectric layer is formed on a first electrode layer. A second dielectric layer having a first trench is formed on the first dielectric layer. Spacers are formed beside sidewalls of the first trench. Apart of the first dielectric layer exposed by the spacers is removed, thereby forming a second trench in the first dielectric layer. A resistance switching material fills in the second trench. The second dielectric layer and the spacers are removed. A second electrode layer is formed on the resistance switching material and the first dielectric layer. The present invention also provides a RRAM formed by said method.

公开(公告)号：US20180047842A1

公开(公告)日：2018-02-15

申请号：US15234525

申请日：2016-08-11

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Liang Yi ,  Shen-De Wang

IPC: H01L29/788 ,  H01L29/40 ,  H01L29/423 ,  H01L29/66 ,  H01L27/115 ,  H01L29/06

CPC classification number: H01L29/66825 ,  H01L21/28273 ,  H01L27/11546 ,  H01L29/42324 ,  H01L29/66545

Abstract: A semiconductor structure and a method for forming the same are provided. The semiconductor structure comprises a substrate, at least a first cell, and at least a second cell. The substrate has a first region and a second region. The first and second cells are in the first and second regions respectively. The first cell comprises a first dielectric layer, a floating gate electrode, an oxide-nitride-oxide (ONO) gate dielectric layer, a second dielectric layer, and a control gate electrode. The ONO gate dielectric layer is on the floating gate electrode in the first dielectric layer on the substrate. The control gate electrode is in both of the first dielectric layer and the second dielectric layer on the first dielectric layer. The ONO gate dielectric layer contacting with the control gate electrode is wholly below a top surface of the first dielectric layer.

公开(公告)号：US09859335B1

公开(公告)日：2018-01-02

申请号：US15367690

申请日：2016-12-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Liang Yi ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L29/00 ,  H01L27/24 ,  H01L29/24 ,  H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/1683

Abstract: A semiconductor device includes an interconnection formed above a substrate, and the interconnection comprising interconnect layers respectively buried in dielectric layers; a lower conducting layer formed above the substrate; a memory cell structure formed on the lower conducting layer and buried in one of the dielectric layers; an upper conducting layer formed on the memory cell structure. The memory cell structure includes a bottom electrode formed on and electrically connected to the lower conducting layer; a transitional metal oxide (TMO) layer formed on the bottom electrode; and a top electrode formed on the TMO layer, wherein the upper conducting layer is formed on the top electrode and electrically connected to the top electrode. Also, the lower conducting layer and the upper conducting layer are positioned in the different dielectric layers.

公开(公告)号：US09806255B1

公开(公告)日：2017-10-31

申请号：US15455142

申请日：2017-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Ching Hsu ,  Liang Yi ,  Shen-De Wang ,  Ko-Chi Chen

IPC: H01L45/00 ,  H01L27/24

CPC classification number: H01L45/1233 ,  H01L27/2463 ,  H01L45/08 ,  H01L45/12 ,  H01L45/124 ,  H01L45/1246 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/16 ,  H01L45/1691

Abstract: A resistive random access memory includes a lower electrode, an upper electrode and a resistive layer between the lower electrode and the upper electrode, wherein the resistive layer includes a constant-resistance portion and a variable-resistance portion surrounding the constant-resistance portion.

公开(公告)号：US09666680B1

公开(公告)日：2017-05-30

申请号：US14944224

申请日：2015-11-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yuan-Hsiang Chang ,  Shen-De Wang ,  Chih-Chien Chang ,  Jianjun Yang ,  Aaron Chen

IPC: H01L29/788 ,  H01L29/423 ,  H01L29/66 ,  H01L21/28 ,  H01L21/265 ,  H01L21/321 ,  H01L21/223 ,  H01L21/285 ,  H01L21/3213 ,  H01L21/311 ,  H01L29/51 ,  H01L27/11521

CPC classification number: H01L29/42328 ,  H01L21/26586 ,  H01L21/28273 ,  H01L21/28562 ,  H01L21/31111 ,  H01L21/321 ,  H01L21/32133 ,  H01L27/11521 ,  H01L28/00 ,  H01L29/42324 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66825 ,  H01L29/788

Abstract: A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.

公开(公告)号：US09508835B2

公开(公告)日：2016-11-29

申请号：US13741399

申请日：2013-01-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Wen-Chung Chang ,  Shen-De Wang ,  Ya-Huei Huang ,  Feng-Ji Tsai ,  Chien-Hung Chen

IPC: H01L27/115 ,  H01L29/66 ,  H01L29/792 ,  H01L29/423 ,  H01L21/28

CPC classification number: H01L29/66833 ,  H01L21/28282 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/4234 ,  H01L29/792

Abstract: A method for manufacturing a non-volatile memory structure includes providing a substrate having a memory region and a logic region defined thereon, masking the logic region while forming at least a first gate in the memory region, forming an oxide-nitride-oxide (ONO) structure under the first gate, forming an oxide structure covering the ONO structure on the substrate, masking the memory region while forming a second gate in the logic region, and forming a first spacer on sidewalls of the first gate and a second spacer on sidewalls of the second gate simultaneously.

Abstract translation: 一种用于制造非易失性存储器结构的方法包括提供具有存储区域和限定在其上的逻辑区域的衬底，在形成存储区域中的至少第一栅极的同时屏蔽逻辑区域，形成氧化物 - 氧化物 - 氧化物（ONO ）结构，在衬底上形成覆盖ONO结构的氧化物结构，在逻辑区域中形成第二栅极的同时掩蔽存储区域，以及在第一栅极的侧壁上形成第一间隔物，在侧壁上形成第二间隔物 的第二个门。

公开(公告)号：US20160049525A1

公开(公告)日：2016-02-18

申请号：US14462550

申请日：2014-08-18

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Weichang Liu ,  Zhen Chen ,  Shen-De Wang ,  Wei Ta ,  Yi-Shan Chiu ,  Yuan-Hsiang Chang

IPC: H01L29/792 ,  H01L29/423 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/66 ,  H01L29/49

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/31105 ,  H01L21/31144 ,  H01L27/11573 ,  H01L29/42344 ,  H01L29/4916 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833

Abstract: A flash memory structure includes a memory gate on a substrate, a select gate adjacent to the memory gate, and an oxide-nitride spacer between the memory gate and the select gate, where the oxide-nitride spacer further includes an oxide layer and a nitride layer having an upper nitride portion and a lower nitride portion, and the upper nitride portion is thinner than the lower nitride portion.

Abstract translation: 闪速存储器结构包括衬底上的存储栅极，与存储栅极相邻的选择栅极以及存储栅极和选择栅极之间的氧化物氮化物间隔物，其中氧化物氮化物间隔物还包括氧化物层和氮化物 层具有上部氮化物部分和下部氮化物部分，并且上部氮化物部分比下部氮化物部分薄。

公开(公告)号：US09111796B2

公开(公告)日：2015-08-18

申请号：US14158875

申请日：2014-01-20

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Zhen Chen ,  Shen-De Wang ,  Yi-Shan Chiu ,  Wei Cheng

IPC: H01L27/115 ,  H01L23/00 ,  H01L27/02 ,  H01L27/105

CPC classification number: H01L27/115 ,  H01L27/0207 ,  H01L27/1052 ,  H01L27/11519 ,  H01L27/11524

Abstract: A layout structure for memory devices includes a plurality of first gate patterns, a plurality of first landing pad patterns, a plurality of dummy patterns, a plurality of second landing pad patterns, and a plurality of second gate patterns. The first landing pad patterns are parallel with each other and electrically connected to the first gate patterns. The dummy patterns and the first landing pad patterns are alternately arranged, and the second landing pad patterns are respectively positioned in between one first landing pad pattern and one dummy pattern. The second gate patterns are electrically connected to the second landing pad patterns.

Abstract translation: 用于存储器件的布局结构包括多个第一栅极图案，多个第一着陆焊盘图案，多个虚设图案，多个第二着陆焊盘图案和多个第二栅极图案。 第一着陆焊盘图案彼此平行并电连接到第一栅极图案。 交替布置虚拟图案和第一着陆焊盘图案，并且第二着陆焊盘图案分别位于一个第一着陆焊盘图案和一个虚设图案之间。 第二栅极图案电连接到第二着陆焊盘图案。