公开(公告)号：US20170046515A1

公开(公告)日：2017-02-16

申请号：US15338598

申请日：2016-10-31

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY

IPC: G06F21/57 ,  H04L9/06

CPC classification number: G06F21/572 ,  G06F2221/2139 ,  H04L9/0631 ,  H04L9/0643

Abstract: An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), a tamper detector, a random number generator, and a JTAG control chain. The BIOS ROM includes BIOS contents stored as plaintext, and an encrypted message digest, where the encrypted message digest has an encrypted version of a first message digest that corresponds to the BIOS contents. The tamper detector is operatively coupled to the BIOS ROM, and is configured to generate a BIOS check interrupt at a combination of prescribed intervals and event occurrences, and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest, and is configured to compare the second message digest with the decrypted message digest, and is configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal, where the event occurrences include input/output accesses. The random number generator disposed within the microprocessor, and generates a random number at completion of a current BIOS check, which is employed to set a following prescribed interval, whereby the prescribed intervals are randomly varied. The JTAG control chain is configured to program the combination of prescribed intervals and event occurrences within tamper detection microcode storage.

Abstract translation: 提供了一种用于保护计算系统中的基本输入/输出系统（BIOS）的装置。 该装置包括BIOS只读存储器（ROM），篡改检测器，随机数发生器和JTAG控制链。 BIOS ROM包括作为明文存储的BIOS内容和加密的消息摘要，其中加密的消息摘要具有对应于BIOS内容的第一消息摘要的加密版本。 篡改检测器可操作地耦合到BIOS ROM，并且被配置为以规定的间隔和事件发生的组合生成BIOS检查中断，并且被配置为在断言BIOS检查中断时访问BIOS内容和加密的消息摘要 并且被配置为引导微处理器产生对应于BIOS内容的第二消息摘要和对应于加密消息摘要的解密消息摘要，并且被配置为将第二消息摘要与解密的消息摘要进行比较，并且被配置为 如果第二消息摘要和解密的消息摘要不相等，则排除微处理器的操作，其中事件发生包括输入/​​输出访问。 布置在微处理器内的随机数发生器，并且在当前BIOS检查完成时产生一个随机数，用于设定以下规定的间隔，由此规定的间隔随机变化。 JTAG控制链被配置为对篡改检测微代码存储器内的规定间隔和事件发生的组合进行编程。

公开(公告)号：US20160349824A1

公开(公告)日：2016-12-01

申请号：US15232506

申请日：2016-08-09

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  STEPHAN GASKINS

IPC: G06F1/32 ,  G06F9/30 ,  G06F12/084 ,  G06F1/12 ,  G06F13/24 ,  G06F12/0875 ,  G06F9/38 ,  G06F1/04

CPC classification number: G06F9/3885 ,  G06F1/04 ,  G06F1/12 ,  G06F1/3203 ,  G06F1/3237 ,  G06F1/324 ,  G06F1/3287 ,  G06F1/3296 ,  G06F9/30032 ,  G06F9/30047 ,  G06F9/30079 ,  G06F9/30087 ,  G06F9/30105 ,  G06F9/30145 ,  G06F9/3802 ,  G06F9/3861 ,  G06F9/4403 ,  G06F9/4405 ,  G06F9/4411 ,  G06F9/4418 ,  G06F12/0808 ,  G06F12/084 ,  G06F12/0875 ,  G06F13/24 ,  G06F13/364 ,  G06F13/42 ,  G06F21/53 ,  G06F21/57 ,  G06F2212/452 ,  G06F2212/6028 ,  G06F2212/62 ,  H01L22/34 ,  H04L9/0877 ,  H04L9/0897 ,  Y02B70/12 ,  Y02B70/123 ,  Y02B70/126 ,  Y02B70/30 ,  Y02D10/10 ,  Y02D10/126 ,  Y02D10/128 ,  Y02D10/13 ,  Y02D10/171 ,  Y02D10/172 ,  Y02D10/30 ,  Y02D50/20

Abstract: A microprocessor a plurality of processing cores, wherein each of the plurality of processing cores instantiates a respective architecturally-visible storage resource. A first core of the plurality of processing cores is configured to encounter an architectural instruction that instructs the first core to update the respective architecturally-visible storage resource of the first core with a value specified by the architectural instruction. The first core is further configured to, in response to encountering the architectural instruction, provide the value to each of the other of the plurality of processing cores and update the respective architecturally-visible storage resource of the first core with the value. Each core of the plurality of processing cores other than the first core is configured to update the respective architecturally-visible storage resource of the core with the value provided by the first core without encountering the architectural instruction.

公开(公告)号：US20160098277A1

公开(公告)日：2016-04-07

申请号：US14569313

申请日：2014-12-12

Applicant: VIA TECHNOLOGIES, INC.

Inventor： MATTHEW DANIEL DAY ,  G. GLENN HENRY ,  TERRY PARKS

IPC: G06F9/38

CPC classification number: G06F9/3814 ,  G06F9/38 ,  G06F9/3836

Abstract: A compressing instruction queue for a microprocessor including a queue and redirect logic. The queue includes a matrix of storage locations including N rows and M columns for storing microinstructions of the microprocessor in sequential order. The redirect logic is configured to receive and write multiple microinstructions per cycle of a clock signal into sequential storage locations of the queue without leaving unused storage locations and beginning at a first available storage location in the queue. The redirect logic performs redirection and compression to eliminate empty locations or holes in the queue and to reduce the number of write ports interfaced with each storage location of the queue.

Abstract translation: 用于微处理器的压缩指令队列，包括队列和重定向逻辑。 队列包括存储位置矩阵，包括N行和M列，用于按顺序存储微处理器的微指令。 重定向逻辑被配置为每个周期的时钟信号接收和写入多个微指令到队列的顺序存储位置，而不留下未使用的存储位置并且从队列中的第一可用存储位置开始。 重定向逻辑执行重定向和压缩以消除队列中的空位置或空洞，并减少与队列的每个存储位置接口的写入端口的数量。

公开(公告)号：US20150338905A1

公开(公告)日：2015-11-26

申请号：US14285448

申请日：2014-05-22

Applicant: Via Technologies, Inc.

Inventor： G. GLENN HENRY ,  DINESH K. JAIN ,  STEPHAN GASKINS

IPC: G06F1/32 ,  G06F12/08 ,  G06F12/12

CPC classification number: G06F3/0631 ,  G06F1/3275 ,  G06F3/0604 ,  G06F3/0625 ,  G06F3/064 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/10 ,  G06F12/08 ,  G06F12/0811 ,  G06F12/0866 ,  G06F12/12 ,  G06F2212/1028 ,  G06F2212/1041 ,  G06F2212/214 ,  G06F2212/281 ,  G06F2212/283 ,  G06F2212/313 ,  G06F2212/601 ,  G06F2212/608 ,  G11C7/20 ,  G11C17/16 ,  G11C17/18 ,  G11C29/787 ,  G11C2029/4402

Abstract: An apparatus includes a fuse array and a stores. The fuse array is programmed with compressed configuration data for a plurality of cores. The stores is coupled to the plurality of cores, and includes a plurality of sub-stores that each correspond to each of the plurality of cores, where one of the plurality of cores accesses the semiconductor fuse array upon power-up/reset to read and decompress the compressed configuration data, and to store a plurality of decompressed configuration data sets for one or more cache memories within the each of the plurality of cores in the plurality of sub-stores. Each of the plurality of cores has sleep logic. The sleep logic is configured to subsequently access a corresponding one of the each of the plurality of sub-stores to retrieve and employ the decompressed configuration data sets to initialize the one or more caches following a power gating event.

Abstract translation: 一种装置包括熔丝阵列和商店。 保险丝阵列用多个核心的压缩配置数据编程。 存储器耦合到多个核心，并且包括多个子存储器，每个子存储器对应于多个核心中的每一个，多个核心中的一个核心在上电/复位时访问半导体熔丝阵列以读取，以及 对压缩的配置数据进行解压缩，并且在多个子存储器中的多个核心的每个内存储一个或多个高速缓存存储器的多个解压配置数据集。 多个核心中的每一个具有睡眠逻辑。 睡眠逻辑被配置为随后访问多个子商店中的每一个的对应的一个，以检索并使用解压配置数据集来初始化电源门控事件之后的一个或多个高速缓存。

公开(公告)号：US20150227372A1

公开(公告)日：2015-08-13

申请号：US14522512

申请日：2014-10-23

Applicant: VIA TECHNOLOGIES, INC.

Inventor： G. GLENN HENRY ,  TERRY PARKS ,  RODNEY E. HOOKER

IPC: G06F9/30 ,  G06F11/07

CPC classification number: G06F9/30145 ,  G06F9/30014 ,  G06F9/30076 ,  G06F9/30185 ,  G06F9/30189 ,  G06F11/0721 ,  G06F11/0793

Abstract: A processor includes a decoder that decodes an instruction that instructs the processor to perform subsequent computations in an approximate manner and a functional unit that performs the subsequent computations in the approximate manner in response to the instruction. An instruction instructs the processor to clear an error amount associated with a value stored in a general purpose register of the processor. The error amount indicates an amount of error associated with a result of a computation performed by the processor in an approximate manner. The processor also clears the error amount in response to the instruction. Another instruction specifies a computation to be performed and includes a prefix that indicates the processor is to perform the computation in an approximate manner. The functional unit performs the computation specified by the instruction in the approximate manner specified by the prefix.

Abstract translation: 一种处理器包括一个译码器，该解码器解码指示处理器以近似方式执行后续计算的指令，以及响应该指令以近似方式执行后续计算的功能单元。 指令指示处理器清除与存储在处理器的通用寄存器中的值相关联的错误量。 错误量表示与处理器以近似的方式执行的计算结果相关联的错误量。 处理器还会根据指令清除错误量。 另一个指令指定要执行的计算，并且包括指示处理器以近似的方式执行计算的前缀。 功能单元以由前缀指定的近似方式执行由指令指定的计算。