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    TRANSISTOR ARCHITECTURE HAVING EXTENDED RECESSED SPACER AND SOURCE/DRAIN REGIONS AND METHOD OF MAKING SAME
    31.
    发明申请
    TRANSISTOR ARCHITECTURE HAVING EXTENDED RECESSED SPACER AND SOURCE/DRAIN REGIONS AND METHOD OF MAKING SAME 有权
    具有延伸的间隔器和源/排水区域的晶体管结构及其制造方法

    公开(公告)号：US20140291737A1

    公开(公告)日：2014-10-02

    申请号：US13995717

    申请日：2013-03-29

    申请人： Walid M. Hafez ,  Joodong Park ,  Jeng-Ya D. Yeh ,  Chia-Hong Jan ,  Curtis Tsai

    发明人： Walid M. Hafez ,  Joodong Park ,  Jeng-Ya D. Yeh ,  Chia-Hong Jan ,  Curtis Tsai

    IPC分类号： H01L29/78 ,  H01L29/66

    CPC分类号： H01L29/785 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78

    摘要： Techniques are disclosed for forming transistor architectures having extended recessed spacer and source/drain (S/D) regions. In some embodiments, a recess can be formed, for example, in the top of a fin of a fin-based field-effect transistor (finFET), such that the recess allows for forming extended recessed spacers and S/D regions in the finFET that are adjacent to the gate stack. In some instances, this configuration provides a higher resistance path in the top of the fin, which can reduce gate-induced drain leakage (GIDL) in the finFET. In some embodiments, precise tuning of the onset of GIDL can be provided. Some embodiments may provide a reduction in junction leakage (Lb) and a simultaneous increase in threshold voltage (VT). The disclosed techniques can be implemented with planar and non-planar fin-based architectures and can be used in standard metal-oxide-semiconductor (MOS) and complementary MOS (CMOS) process flows, in some embodiments.

    摘要翻译： 公开了用于形成具有延伸的凹入间隔物和源极/漏极（S / D）区域的晶体管架构的技术。 在一些实施例中，可以例如在鳍式场效应晶体管（finFET）的鳍的顶部形成凹部，使得凹部允许在鳍状物FET中形成延伸的凹入的间隔物和S / D区域 它们与栅极堆叠相邻。 在一些情况下，该配置在鳍的顶部提供更高的电阻路径，这可以减少finFET中的栅极引起的漏极泄漏（GIDL）。 在一些实施例中，可以提供GIDL的开始的精确调整。 一些实施例可以提供结漏电（Lb）的降低和阈值电压（VT）的同时增加。 所公开的技术可以用平面和非平面鳍状结构来实现，并且在一些实施例中可以用于标准金属氧化物半导体（MOS）和互补MOS（CMOS）工艺流程中。

    Penetrating implant for forming a semiconductor device
    32.
    发明授权
    Penetrating implant for forming a semiconductor device 有权
    用于形成半导体器件的穿透植入物

    公开(公告)号：US08426927B2

    公开(公告)日：2013-04-23

    申请号：US13107783

    申请日：2011-05-13

    申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    IPC分类号： H01L29/66 ,  H01L21/02

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

    摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

    摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

    Precision resistor for non-planar semiconductor device architecture
    34.
    发明授权
    Precision resistor for non-planar semiconductor device architecture 有权
    用于非平面半导体器件结构的精密电阻器

    公开(公告)号：US08889508B2

    公开(公告)日：2014-11-18

    申请号：US14313678

    申请日：2014-06-24

    申请人： Jeng-Ya D. Yeh ,  Peter J. Vandervoorn ,  Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park

    发明人： Jeng-Ya D. Yeh ,  Peter J. Vandervoorn ,  Walid M. Hafez ,  Chia-Hong Jan ,  Curtis Tsai ,  Joodong Park

    IPC分类号： H01L21/8234 ,  H01L29/66 ,  H01L49/02

    CPC分类号： H01L21/823431 ,  H01L27/0629 ,  H01L27/0886 ,  H01L28/20 ,  H01L29/66545 ,  H01L29/66795

    摘要： Precision resistors for non-planar semiconductor device architectures are described. In a first example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. A resistor structure is disposed above the first semiconductor fin but not above the second semiconductor fin. A transistor structure is formed from the second semiconductor fin but not from the first semiconductor fin. In a second example, a semiconductor structure includes first and second semiconductor fins disposed above a substrate. An isolation region is disposed above the substrate, between the first and second semiconductor fins, and at a height less than the first and second semiconductor fins. A resistor structure is disposed above the isolation region but not above the first and second semiconductor fins. First and second transistor structures are formed from the first and second semiconductor fins, respectively.

    摘要翻译： 描述了用于非平面半导体器件结构的精密电阻器。 在第一示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。 电阻器结构设置在第一半导体鳍片上方，但不在第二半导体鳍片之上。 晶体管结构由第二半导体鳍形成，但不由第一半导体鳍形成。 在第二示例中，半导体结构包括设置在基板上方的第一和第二半导体翅片。 隔离区设置在基板之上，位于第一和第二半导体鳍之间，并且在小于第一和第二半导体鳍片的高度处。 电阻结构设置在隔离区域上方，但不在第一和第二半导体鳍片之上。 第一和第二晶体管结构分别由第一和第二半导体鳍形成。

    Penetrating implant for forming a semiconductor device
    35.
    发明授权
    Penetrating implant for forming a semiconductor device 失效
    用于形成半导体器件的穿透植入物

    公开(公告)号：US08741720B2

    公开(公告)日：2014-06-03

    申请号：US13857578

    申请日：2013-04-05

    申请人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    发明人： Giuseppe Curello ,  Ian R. Post ,  Nick Lindert ,  Walid M. Hafez ,  Chia-Hong Jan ,  Mark T. Bohr

    IPC分类号： H01L21/336

    CPC分类号： H01L29/66477 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823456 ,  H01L21/823493 ,  H01L29/6659 ,  H01L29/7833 ,  Y10S438/918

    摘要： A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.

    摘要翻译： 描述了形成半导体器件的半导体器件和方法。 半导体包括设置在基板上的栅极堆叠。 尖端区域设置在栅极堆叠的任一侧上的衬底中。 卤素区域设置在邻近尖端区域的衬底中。 阈值电压注入区域直接设置在栅极堆叠的正下方的衬底中。 特定导电类型的掺杂剂杂质原子的浓度在阈值电压注入区域中在晕圈区域中大致相同。 该方法包括掺杂剂杂质注入技术，其具有足够的强度以穿透栅极堆叠。

    Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection
    40.
    发明授权
    Extended drain non-planar MOSFETs for electrostatic discharge (ESD) protection 有权
    用于静电放电（ESD）保护的扩展漏极非平面MOSFET

    公开(公告)号：US09087719B2

    公开(公告)日：2015-07-21

    申请号：US13631586

    申请日：2012-09-28

    申请人： Akm Ahsan ,  Walid M. Hafez

    发明人： Akm Ahsan ,  Walid M. Hafez

    IPC分类号： H02H9/00 ,  H01L27/088 ,  H01L27/02 ,  H02H9/04 ,  H01L27/12 ,  H02H1/04 ,  H02H3/22

    CPC分类号： H02H9/046 ,  H01L27/027 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/7833 ,  H01L29/7835 ,  H01L29/7851 ,  H01L2924/0002 ,  H02H3/22 ,  H01L2924/00

    摘要： Snapback ESD protection device employing one or more non-planar metal-oxide-semiconductor transistors (MOSFETs) are described. The ESD protection devices may further include lightly-doped extended drain regions, the resistances of which may be capacitively controlled through control gates independent of a gate electrode held at a ground potential. Control gates may be floated or biased to modulate ESD protection device performance. In embodiments, a plurality of core circuits are protected with a plurality of non-planar MOSFET-based ESD protection devices with control gate potentials varying across the plurality.

    摘要翻译： 描述采用一个或多个非平面金属氧化物半导体晶体管（MOSFET）的Snapback ESD保护装置。 ESD保护器件还可以包括轻掺杂的延伸漏极区，其电阻可以通过独立于保持在接地电位的栅电极的控制栅电容地控制。 控制栅极可以浮置或偏置以调制ESD保护器件的性能。 在实施例中，多个核心电路被多个非平面的基于MOSFET的ESD保护器件保护，其中控制栅极电位在多个上变化。