公开(公告)号：US06537361B2

公开(公告)日：2003-03-25

申请号：US09822637

申请日：2001-03-30

申请人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Fengyan Zhang ,  Jer-Shen Maa ,  Sheng Teng Hsu

IPC分类号： H01L2122

CPC分类号： H01L21/02197 ,  C01G21/00 ,  C01P2002/86 ,  H01L21/02112 ,  H01L21/02175 ,  H01L21/02282 ,  H01L21/31604 ,  H01L21/31691

摘要： A method of synthesizing a PGO spin-coating precursor solution includes utilizing the starting materials of lead acetate trihydrate (Pb(OAc)2•3H2O) and germanium alkoxide (Ge(OR)4(R=C2H5 and CH(CH3)2)). The organic solvent is di(ethylene glycol) ethyl ether. The mixed solution of lead and di(ethylene glycol) ethyl ether is heated in an atmosphere of air at a temperature no greater than 185° C., and preferably no greater than 190° C. for a time period in a range of thirty minutes to four hours. During the heating step the color of the solution is monitored to determine when the reaction is complete and when decomposition of the desired product begins to take place. The solution is then added to germanium di(ethylene glycol) ethyl ether to make the PGO spin-coating solution. This second step also entails heating the solution to a temperature no greater than 190° C. for a time period in a range of 0.5 to 2.0 hours. The process results in a PGO precursor solution suitable for use in spin-coating.

公开(公告)号：US07696550B2

公开(公告)日：2010-04-13

申请号：US11805177

申请日：2007-05-22

申请人： Tingkai Li ,  Lawrence J. Charneski ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Lawrence J. Charneski ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L29/76

CPC分类号： H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1616

摘要： A multi-layer PrxCa1-xMnO3 (PCMO) thin film capacitor and associated deposition method are provided for forming a bipolar switching thin film. The method comprises: forming a bottom electrode; depositing a nanocrystalline PCMO layer; depositing a polycrystalline PCMO layer; forming a multi-layer PCMO film with bipolar switching properties; and, forming top electrode overlying the PCMO film. If the polycrystalline layers are deposited overlying the nanocrystalline layers, a high resistance can be written with narrow pulse width, negative voltage pulses. The PCMO film can be reset to a low resistance using a narrow pulse width, positive amplitude pulse. Likewise, if the nanocrystalline layers are deposited overlying the polycrystalline layers, a high resistance can be written with narrow pulse width, positive voltage pulses, and reset to a low resistance using a narrow pulse width, negative amplitude pulse.

摘要翻译： 提供多层PrxCa1-xMnO3（PCMO）薄膜电容器和相关的沉积方法用于形成双极开关薄膜。 该方法包括：形成底部电极; 沉积纳米晶体PCMO层; 沉积多晶PCMO层; 形成具有双极开关特性的多层PCMO膜; 并且形成覆盖PCMO膜的顶部电极。 如果多晶层沉积在纳米晶层之上，则可以用窄脉冲宽度，负电压脉冲写入高电阻。 PCMO膜可以使用窄脉冲宽度，正幅度脉冲复位为低电阻。 同样，如果纳米晶层沉积在多晶层上，则可以用窄脉冲宽度，正电压脉冲写入高电阻，并使用窄脉冲宽度，负幅度脉冲将其复位为低电阻。

公开(公告)号：US07157287B2

公开(公告)日：2007-01-02

申请号：US10855088

申请日：2004-05-27

申请人： Wei-Wei Zhuang ,  Tingkai Li ,  Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

发明人： Wei-Wei Zhuang ,  Tingkai Li ,  Wei Pan ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L21/20

CPC分类号： C23C18/1216 ,  C23C18/1225 ,  C23C18/1241 ,  C23C18/1283 ,  C30B23/02 ,  C30B29/24 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1608

摘要： A method of fabricating a CMR thin film for use in a semiconductor device includes preparing a CMR precursor in the form of a metal acetate based acetic acid solution; preparing a wafer; placing a wafer in a spin-coating chamber; spin-coating and heating the wafer according to the following: injecting the CMR precursor into a spin-coating chamber and onto the surface of the wafer in the spin-coating chamber; accelerating the wafer to a spin speed of between about 1500 RPM to 3000 RPM for about 30 seconds; baking the wafer at a temperature of about 180° C. for about one minute; ramping the temperature to about 230° C.; baking the wafer for about one minute at the ramped temperature; annealing the wafer at about 500° C. for about five minutes; repeating said spin-coating and heating steps at least three times; post-annealing the wafer at between about 500° C. to 600° C. for between about one to six hours in dry, clean air; and completing the semiconductor device.

摘要翻译： 制造用于半导体器件的CMR薄膜的方法包括制备基于金属乙酸酯的乙酸溶液形式的CMR前体; 准备晶圆; 将晶片放置在旋涂室中; 根据以下步骤旋涂和加热晶片：将CMR前体注入旋涂室并在旋涂室中的晶片表面上; 将晶片加速至约1500RPM至3000RPM之间的旋转速度约30秒; 在约180℃的温度下烘烤晶片约1分钟; 将温度升高至约230℃; 在升温下烘烤晶片约1分钟; 在约500℃退火晶片约5分钟; 重复所述旋涂和加热步骤至少三次; 在约500℃至600℃之间将晶片退火约1至6小时，在干燥，干净的空气中进行退火; 并完成半导体器件。

公开(公告)号：US07042066B2

公开(公告)日：2006-05-09

申请号：US11039536

申请日：2005-01-19

申请人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： H01L29/00

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/101 ,  H01L27/24

摘要： A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si layer overlying the p-Si substrate; prior to forming the n+ Si bit lines, forming a p+ Si layer overlying the n+ Si layer; forming a layer of silicon nitride overlying the p+ layer; forming a top oxide layer overlying the silicon nitride layer; performing a first selective etch of the top oxide layer, the silicon nitride layer, the p+ Si layer, and a portion of the n+ Si layer, to form n+ Si bit lines and bit line trenches between the bit lines; forming an array of metal bottom electrodes overlying a plurality of n-doped silicon (n+ Si) bit lines, with intervening p-doped (p+) Si areas; forming a plurality of word line oxide isolation structures orthogonal to and overlying the n+ Si bit lines, adjacent to the bottom electrodes, and separating the p+ Si areas; forming a plurality of top electrode word lines, orthogonal to the n+ Si bit lines, with an interposing memory resistor material overlying the bottom electrodes; and, forming oxide-filled word line trenches adjacent the word lines.

摘要翻译： 已经提供了存储器阵列双沟槽隔离结构及其形成方法。 该方法包括：形成p掺杂硅（p-Si）衬底; 形成覆盖p-Si衬底的n掺杂（n +）Si层; 在形成n + Si位线之前，形成覆盖n + Si层的p + Si层; 形成覆盖p +层的氮化硅层; 形成覆盖所述氮化硅层的顶部氧化物层; 执行顶部氧化物层，氮化硅层，p + Si层和n + Si层的一部分的第一选择性蚀刻，以在位线之间形成n + Si位线和位线沟槽; 形成覆盖多个n掺杂硅（n + Si）位线的金属底部电极阵列，具有中间p掺杂（p +）Si区域; 形成与所述n + Si位线正交并覆盖与所述底部电极相邻并分离所述p + Si区域的多个字线氧化物隔离结构; 形成与n + Si位线正交的多个顶部电极字线，覆盖在底部电极上的插入式存储电阻材料; 并且在字线附近形成氧化物填充的字线沟槽。

公开(公告)号：US06972239B1

公开(公告)日：2005-12-06

申请号：US10923529

申请日：2004-08-20

申请人： Tingkai Li ,  Wei-Wei Zhuang ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

发明人： Tingkai Li ,  Wei-Wei Zhuang ,  Lawrence J. Charneski ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： C23C16/40 ,  H01L21/20 ,  H01L45/00

CPC分类号： H01L45/1616 ,  C23C16/40 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： A method of fabricating a PCMO thin film at low temperature for use in a RRAM device includes preparing a PCMO precursor; preparing a substrate; placing the substrate into a MOCVD chamber; introducing the PCMO precursor into the MOCVD chamber to deposit a PCMO thin film on the substrate; maintaining a MOCVD vaporizer at between about 240° C. to 280° C. and maintaining the MOCVD chamber at a temperature of between about 300° C. to 400° C.; removing the PCMO thin-film bearing substrate from the MOCVD chamber; and completing the RRAM device.

摘要翻译： 在低温下制造用于RRAM器件的PCMO薄膜的方法包括制备PCMO前体; 制备底物; 将基板放置在MOCVD室中; 将PCMO前体引入MOCVD室以在衬底上沉积PCMO薄膜; 将MOCVD蒸发器保持在约240℃至280℃之间并将MOCVD室保持在约300℃至400℃之间的温度下; 从MOCVD室中取出PCMO薄膜轴承衬底; 并完成RRAM设备。

公开(公告)号：US06921671B1

公开(公告)日：2005-07-26

申请号：US10784669

申请日：2004-02-23

申请人： Fengyan Zhang ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Wei-Wei Zhuang ,  Sheng Teng Hsu

IPC分类号： H01L21/00 ,  H01L21/02

CPC分类号： H01L28/65 ,  H01L28/55

摘要： A method of fabricating a ferroelectric thin film on an iridium-composite electrode in an integrated circuit device includes preparing a substrate; depositing an iridium-composite bottom electrode on the substrate; annealing the bottom electrode in a first annealing step; depositing a buffer layer on the bottom electrode, including depositing a layer of material taken from the group of materials consisting of HfO2, ZrO2, TiO2, LaOx, La—Al—O, Ti—Al—O, Hf—Al—O, Zr—Al—O, Hf—Zr—O, Zr—Ti—O, Hf—Ti—O, La—Zr—O, La—Hf—O, and La—Ti—O; annealing the buffer layer in a second annealing step; depositing a layer of Bi4Ti3O12, to a thickness of between about 20 nm to 500 nm, on the buffer layer; annealing the ferroelectric layer in a third annealing step; and completing the integrated circuit device.

摘要翻译： 在集成电路器件中的铱复合电极上制造铁电薄膜的方法包括：制备衬底; 在基板上沉积铱复合底部电极; 在第一退火步骤中退火底部电极; 在底部电极上沉​​积缓冲层，包括沉积从由HfO 2，ZrO 2，TiO 2，TiO 2，ZrO 2，TiO 2， La，Al-O，Ti-Al-O，Hf-Al-O，Zr-Al-O，Hf-Zr-O，Zr-Ti-O，Hf -Ti-O，La-Zr-O，La-Hf-O和La-Ti-O; 在第二退火步骤中退火缓冲层; 在缓冲层上沉积一层厚度为约20nm至500nm的Bi 4 N 3 O 12 O 12层; 在第三退火步骤中退火铁电层; 并完成集成电路设备。

公开(公告)号：US06875651B2

公开(公告)日：2005-04-05

申请号：US10350643

申请日：2003-01-23

申请人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei Pan ,  Wei-Wei Zhuang

IPC分类号： H01L21/76 ,  G11C13/00 ,  H01L21/3205 ,  H01L21/8246 ,  H01L23/52 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L43/08 ,  H01L21/8234

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/101 ,  H01L27/24

摘要： A memory array dual-trench isolation structure and a method for forming the same have been provided. The method comprises: forming a p-doped silicon (p-Si) substrate; forming an n-doped (n+) Si layer overlying the p-Si substrate; prior to forming the n+ Si bit lines, forming a p+ Si layer overlying the n+ Si layer; forming a layer of silicon nitride overlying the p+ layer; forming a top oxide layer overlying the silicon nitride layer; performing a first selective etch of the top oxide layer, the silicon nitride layer, the p+ Si layer, and a portion of the n+ Si layer, to form n+ Si bit lines and bit line trenches between the bit lines; forming an array of metal bottom electrodes overlying a plurality of n-doped silicon (n+ Si) bit lines, with intervening p-doped (p+) Si areas; forming a plurality of word line oxide isolation structures orthogonal to and overlying the n+ Si bit lines, adjacent to the bottom electrodes, and separating the p+ Si areas; forming a plurality of top electrode word lines, orthogonal to the n+ Si bit lines, with an interposing memory resistor material overlying the bottom electrodes; and, forming oxide-filled word line trenches adjacent the word lines.

摘要翻译： 已经提供了存储器阵列双沟槽隔离结构及其形成方法。 该方法包括：形成p掺杂硅（p-Si）衬底; 形成覆盖p-Si衬底的n掺杂（n +）Si层; 在形成n + Si位线之前，形成覆盖n + Si层的p + Si层; 形成覆盖p +层的氮化硅层; 形成覆盖所述氮化硅层的顶部氧化物层; 执行顶部氧化物层，氮化硅层，p + Si层和n + Si层的一部分的第一选择性蚀刻，以在位线之间形成n + Si位线和位线沟槽; 形成覆盖多个n掺杂硅（n + Si）位线的金属底部电极阵列，具有中间p掺杂（p +）Si区域; 形成与所述n + Si位线正交并覆盖与所述底部电极相邻并分离所述p + Si区域的多个字线氧化物隔离结构; 形成与n + Si位线正交的多个顶部电极字线，覆盖在底部电极上的插入式存储电阻材料; 并且在字线附近形成氧化物填充的字线沟槽。

公开(公告)号：US06861687B2

公开(公告)日：2005-03-01

申请号：US10345547

申请日：2003-01-15

申请人： Sheng Teng Hsu ,  Wei-Wei Zhuang

发明人： Sheng Teng Hsu ,  Wei-Wei Zhuang

IPC分类号： H01L27/115 ,  G11C11/15 ,  G11C11/56 ,  G11C13/00 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/24 ,  H01L43/08 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： G11C11/15 ,  G11C11/16 ,  G11C11/5685 ,  G11C13/0007 ,  G11C13/004 ,  G11C2213/31 ,  G11C2213/77 ,  H01L27/2472 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147

摘要： Resistive cross point memory devices are provided, along with methods of manufacture and use. The memory device comprises an active layer of perovskite material interposed between upper electrodes and lower electrodes. A bit region located within the active layer at the cross point of an upper electrode and a lower electrode has a resistivity that can change through a range of values in response to application of one, or more, voltage pulses. Voltage pulses may be used to increase the resistivity of the bit region, decrease the resistivity of the bit region, or determine the resistivity of the bit region. Memory circuits are provided to aid in the programming and read out of the bit region.

摘要翻译： 提供了电阻式交叉点存储器件以及制造和使用方法。 存储器件包括插在上电极和下电极之间的钙钛矿材料的有源层。 在上电极和下电极的交叉点处位于有源层内的位区域具有响应于施加一个或更多个电压脉冲而可以在值范围内变化的电阻率。 可以使用电压脉冲来增加比特区域的电阻率，降低比特区域的电阻率，或者确定比特区域的电阻率。 提供存储器电路以帮助编程和读出位区域。

公开(公告)号：US06849891B1

公开(公告)日：2005-02-01

申请号：US10730584

申请日：2003-12-08

申请人： Sheng Teng Hsu ,  Wei Pan ,  Fengyan Zhang ,  Wei-Wei Zhuang ,  Tingkai Li

发明人： Sheng Teng Hsu ,  Wei Pan ,  Fengyan Zhang ,  Wei-Wei Zhuang ,  Tingkai Li

IPC分类号： H01L21/28 ,  G11C13/00 ,  G11C16/02 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L27/22 ,  H01L29/68 ,  H01L39/00 ,  H01L43/08 ,  H01L45/00 ,  H01L29/94

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  G11C2213/77 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/147 ,  H01L45/1675

摘要： A RRAM memory cell is formed on a silicon substrate having a operative junction therein and a metal plug formed thereon, includes a first oxidation resistive layer; a first refractory metal layer; a CMR layer; a second refractory metal layer; and a second oxidation resistive layer. A method of fabricating a multi-layer electrode RRAM memory cell includes preparing a silicon substrate; forming a junction in the substrate taken from the group of junctions consisting of N+ junctions and P+ junctions; depositing a metal plug on the junction; depositing a first oxidation resistant layer on the metal plug; depositing a first refractory metal layer on the first oxidation resistant layer; depositing a CMR layer on the first refractory metal layer; depositing a second refractory metal layer on the CMR layer; depositing a second oxidation resistant layer on the second refractory metal layer; and completing the RRAM memory cell.

摘要翻译： 在其上具有工作结的硅衬底上形成有一个RRAM存储单元和形成在其上的金属插塞，包括第一氧化电阻层; 第一难熔金属层; 一个CMR层; 第二难熔金属层; 和第二氧化电阻层。 制造多层电极RRAM存储单元的方法包括制备硅衬底; 从由N +结和P +结组成的接头组中形成在衬底中的结; 在接头上沉积金属塞; 在金属插塞上沉积第一抗氧化层; 在第一耐氧化层上沉积第一难熔金属层; 在第一难熔金属层上沉积CMR层; 在CMR层上沉积第二难熔金属层; 在所述第二难熔金属层上沉积第二抗氧化层; 并完成RRAM存储单元。

公开(公告)号：US06774054B1

公开(公告)日：2004-08-10

申请号：US10640728

申请日：2003-08-13

申请人： Fengyan Zhang ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

发明人： Fengyan Zhang ,  Wei-Wei Zhuang ,  David R. Evans ,  Sheng Teng Hsu

IPC分类号： H01L2131

CPC分类号： G11C13/0007 ,  G11C2213/31 ,  H01L21/31691 ,  H01L28/20 ,  H01L45/04 ,  H01L45/1233 ,  H01L45/147 ,  H01L45/1608

摘要： A method of forming a PCMO thin film in a RRAM device includes preparing a substrate; depositing a metal barrier layer on the substrate; forming a bottom electrode on the barrier layer; spin-coating a layer of Pr1−xCaxMnO3 (PCMO) on the bottom electrode using a PCMO precursor; baking the PCMO thin film in one or more baking steps; annealing the PCMO thin film in a first annealing step after each spin-coating step; repeating the spin-coating step, the baking step and the first annealing step until the PCMO thin film has a desired thickness; annealing the PCMO thin film in a second annealing step, thereby producing a PCMO thin film having a crystalline structure of Pr1−xCaxMnO3, where 0.2

摘要翻译： 在RRAM器件中形成PCMO薄膜的方法包括：制备衬底; 在衬底上沉积金属阻挡层; 在阻挡层上形成底部电极; 使用PCMO前体在底部电极上旋涂一层Pr1-xCaxMnO3（PCMO）; 在一个或多个烘烤步骤中烘烤PCMO薄膜; 在每个旋涂步骤之后的第一退火步骤中对PCMO薄膜进行退火; 重复旋涂步骤，烘烤步骤和第一退火步骤直到PCMO薄膜具有所需厚度; 在第二退火步骤中退火PCMO薄膜，从而制备具有Pr1-xCaxMnO3晶体结构的PCMO薄膜，其中0.2 <= X <= 0.5; 沉积顶部电极; 图案化顶部电极; 并完成RRAM设备。