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    Embedded semiconductor device and method of manufacturing an embedded semiconductor device
    31.
    发明申请
    Embedded semiconductor device and method of manufacturing an embedded semiconductor device 审中-公开
    嵌入式半导体器件及其制造方法

    公开(公告)号：US20090065845A1

    公开(公告)日：2009-03-12

    申请号：US12230938

    申请日：2008-09-08

    Applicant: Young-Ho Kim ,  Hee-Seog Jeon ,  Yong-Kyu Lee

    Inventor： Young-Ho Kim ,  Hee-Seog Jeon ,  Yong-Kyu Lee

    IPC: H01L27/115 ,  H01L21/8247

    CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11529 ,  H01L29/665 ,  H01L29/7833

    Abstract: Provided are an embedded semiconductor device and a method of manufacturing an embedded semiconductor device. In a method of manufacturing the embedded semiconductor device, layers of at least one cell gate stack may be formed in a cell area of a substrate. A logic gate structure may be formed in a logic area of the substrate. First source/drain regions may be formed adjacent to the logic gate structure, and metal silicide patterns may be formed on the logic gate structure and the first source/drain regions. At least one hard mask may be formed on the layers of the at least one cell gate stack, and a blocking pattern may be formed to cover the logic gate structure and the first source/drain regions. The at least one cell gate stack may be formed in the cell area by etching the layers of the at least one cell gate stack using the at least one hard mask as an etching mask. A memory transistor in the cell area may have an increased integration degree and a logic transistor in the logic area may have an increased response speed and a decreased resistance.

    Abstract translation: 提供了嵌入式半导体器件和制造嵌入式半导体器件的方法。 在制造嵌入式半导体器件的方法中，可以在衬底的单元区域中形成至少一个单元栅极堆叠的层。 逻辑门结构可以形成在衬底的逻辑区域中。 可以在逻辑门结构附近形成第一源极/漏极区，并且可以在逻辑门结构和第一源极/漏极区上形成金属硅化物图案。 可以在至少一个单元栅极堆叠的层上形成至少一个硬掩模，并且可以形成阻挡图案以覆盖逻辑门结构和第一源极/漏极区域。 可以通过使用至少一个硬掩模作为蚀刻掩模来蚀刻至少一个单元栅极堆叠的层而在单元区域中形成至少一个单元栅极堆叠。 单元区域中的存储晶体管可以具有增加的积分度，并且逻辑区域中的逻辑晶体管可以具有增加的响应速度和降低的电阻。

    MASK ROM DEVICES AND METHODS FOR FORMING THE SAME
    32.
    发明申请
    MASK ROM DEVICES AND METHODS FOR FORMING THE SAME 审中-公开
    掩模ROM器件及其形成方法

    公开(公告)号：US20080179692A1

    公开(公告)日：2008-07-31

    申请号：US12013618

    申请日：2008-01-14

    Applicant: Myung-Jo Chun ,  Hee-Seog Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

    Inventor： Myung-Jo Chun ,  Hee-Seog Jeon ,  Yong-Kyu Lee ,  Young-Ho Kim

    IPC: H01L27/112 ,  H01L21/8234

    CPC classification number: H01L27/11293 ,  H01L27/105 ,  H01L27/112 ,  H01L27/11266 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/665

    Abstract: A mask read only memory (MROM) device includes first and second gate electrodes formed at on-cell and off-cell regions of a substrate, respectively. A first impurity region is formed at the on-cell region of the substrate so as to be adjacent the first gate electrode. A second impurity region including the same conductivity type as that of the first impurity region is formed at the off-cell region of the substrate so as to be spaced apart from a sidewall of the second gate electrode. A fourth impurity region is formed at the off-cell region to extend from the second impurity region and to overlap with the sidewall of the second gate electrode. The fourth impurity region has a conductivity type opposite to that of the second impurity region and a depth greater than that of the second impurity region.

    Abstract translation: 掩模只读存储器（MROM）器件分别包括形成在衬底的单元和离子区域的第一和第二栅电极。 第一杂质区形成在基板的单电池区域上，以便与第一栅电极相邻。 形成与第一杂质区相同导电类型的第二杂质区，以与第二栅电极的侧壁间隔开。 第四杂质区形成在离电池区域，从第二杂质区延伸并与第二栅电极的侧壁重叠。 第四杂质区域具有与第二杂质区域相反的导电类型，并且深度大于第二杂质区域的深度。

    Mask ROM and method of fabricating the same
    33.
    发明申请
    Mask ROM and method of fabricating the same 有权
    掩模ROM及其制造方法

    公开(公告)号：US20080003810A1

    公开(公告)日：2008-01-03

    申请号：US11823381

    申请日：2007-06-27

    Applicant: Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

    Inventor： Yong-Kyu Lee ,  Hee-Seog Jeon ,  Jeong-Uk Han ,  Young-Ho Kim ,  Myung-Jo Chun

    IPC: H01L21/4763

    CPC classification number: H01L27/1021

    Abstract: A mask read-only memory (ROM) includes a dielectric layer formed on a substrate and a plurality of first conductive lines formed on the dielectric layer. A plurality of diodes are formed in the first conductive lines, and a plurality of final vias are formed for a first set of the diodes each representing a first type of memory cell, with no final via being formed for a second set of diodes each representing a second type of memory cell. Each of a plurality of second conductive lines is formed over a column of the diodes.

    Abstract translation: 掩模只读存储器（ROM）包括形成在基板上的电介质层和形成在电介质层上的多个第一导电线。 在第一导线中形成多个二极管，并且为第一组二极管形成多个最终通孔，每个二极管表示第一类型的存储单元，没有形成用于第二组二极管的最终通孔，每个二极管表示 第二种类型的存储单元。 多个第二导电线中的每一个形成在二极管的列上。

    Non-volatile semiconductor device with anti-punch through regions
    35.
    发明授权
    Non-volatile semiconductor device with anti-punch through regions 有权
    具有抗穿透区域的非易失性半导体器件

    公开(公告)号：US06563168B2

    公开(公告)日：2003-05-13

    申请号：US09989113

    申请日：2001-11-21

    Applicant: Yong-Kyu Lee

    Inventor： Yong-Kyu Lee

    IPC: H01L29788

    CPC classification number: H01L27/11543 ,  H01L21/84 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11546 ,  H01L27/1203 ,  H01L29/66825

    Abstract: A non-volatile semiconductor device and a method of making such a device having a memory cell formation part and a peripheral circuit part having high and low-voltage transistor formation parts, wherein the device includes an anti-punch through region surrounding a drain region in the memory cell formation part, and surrounding drain and source regions of the low-voltage transistor formation part.

    Abstract translation: 一种非易失性半导体器件及其制造方法，该器件具有存储单元形成部分和具有高电压和低电压晶体管形成部分的外围电路部分，其中该器件包括围绕漏极区域的反穿通区域 存储单元形成部分以及低压晶体管形成部分的周围的漏极和源极区域。

    Magnetic memory devices including shared lines
    38.
    发明授权
    Magnetic memory devices including shared lines 有权
    包括共享线路的磁存储器件

    公开(公告)号：US09318181B2

    公开(公告)日：2016-04-19

    申请号：US14448717

    申请日：2014-07-31

    Applicant: Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Kee-Moon Chun ,  Hee-Seog Jeon

    Inventor： Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Kee-Moon Chun ,  Hee-Seog Jeon

    IPC: G11C11/00 ,  G11C11/16

    CPC classification number: G11C11/1675 ,  G11C11/16 ,  G11C11/1659

    Abstract: A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.

    Abstract translation: 磁存储装置包括字线，与字线交叉的位线，设置在字线和位线之间的交叉处的磁存储元件，以及连接到字线的选择晶体管。 磁存储元件在多个字线之间共享字线，并且共享连接到在选择晶体管之间共享的字线的选择晶体管。 还描述了相关系统和操作方法。

    Magnetic Memory Devices Including Magnetic Memory Cells Having Opposite Magnetization Directions
    39.
    发明申请
    Magnetic Memory Devices Including Magnetic Memory Cells Having Opposite Magnetization Directions 有权
    包括具有相反磁化方向的磁记忆体的磁存储器件

    公开(公告)号：US20150179244A1

    公开(公告)日：2015-06-25

    申请号：US14509756

    申请日：2014-10-08

    Applicant: Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Hee-Seog Jeon

    Inventor： Bo-Young Seo ,  Yong-Kyu Lee ,  Choong-Jae Lee ,  Hee-Seog Jeon

    IPC: G11C11/16

    CPC classification number: G11C11/161 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/1675

    Abstract: A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.

    Abstract translation: 磁存储器件包括分别耦合到第一和第二位线的第一和第二磁存储器单元。 第一和第二磁存储单元分别包括钉扎磁性层，自由磁性层和隧道绝缘层。 固定磁性层，隧道绝缘层和自由磁性层的各个堆叠顺序在第一和第二磁性存储单元中是不同的。 磁存储器件还包括至少一个晶体管，其被配置为将第一和第二磁存储器单元耦合到公共源极线。 还讨论了相关的操作方法。

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