公开(公告)号：US09122649B2

公开(公告)日：2015-09-01

申请号：US14048114

申请日：2013-10-08

Applicant: International Business Machines Corporation

Inventor： Utz Bacher

IPC: G06F15/173 ,  G06F9/54

CPC classification number: G06F12/1009 ,  G06F9/541 ,  G06F9/545 ,  G06F9/547 ,  G06F12/084 ,  G06F15/17331 ,  G06F2212/314 ,  G06F2212/684

Abstract: A method and computing system for handling a page fault while executing a cross-platform system call with a shared page cache. A first kernel running in a first computer system receives a request for a faulted page associated with raw data from a second kernel running in a second computer system. In response to the request for the faulted page: (i) a first validity flag is updated to denote that the faulted page is unavailable to the first computer system in a first copy of the shared page cache and (ii) the faulted page is transmitted to the second kernel for insertion of the faulted page in a second copy of the shared page cache and for updating a second validity flag to denote that the faulted page is available to the second computer system in the second copy of the shared page cache.

Abstract translation: 一种在使用共享页面缓存执行跨平台系统调用时处理页面错误的方法和计算系统。 在第一计算机系统中运行的第一内核从在第二计算机系统中运行的第二内核接收与原始数据相关联的故障页面的请求。 响应于对故障页面的请求：（i）更新第一有效性标志以表示故障页面在共享页面高速缓存的第一副本中对第一计算机系统不可用，并且（ii）发送故障页面 所述第二内核用于将所述故障页面插入所述共享页面高速缓存的第二副本中，并且用于更新第二有效性标志以指示所述故障页面在所述共享页面高速缓存的第二副本中对于所述第二计算机系统可用。

公开(公告)号：US09086958B2

公开(公告)日：2015-07-21

申请号：US13837997

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Jason W. Brandit ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC: G06F12/00 ,  G06F12/02 ,  G06F9/48 ,  G06F12/10 ,  G06F9/455

CPC classification number: G06F12/1036 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4843 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1063 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/30 ,  G06F2212/50 ,  G06F2212/604 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

公开(公告)号：US20150113200A1

公开(公告)日：2015-04-23

申请号：US14579526

申请日：2014-12-22

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC: G06F12/02

CPC classification number: G06F12/1036 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4843 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1063 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/30 ,  G06F2212/50 ,  G06F2212/604 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

公开(公告)号：US20140281249A1

公开(公告)日：2014-09-18

申请号：US13799942

申请日：2013-03-13

Applicant: CLOUD PHYSICS, INC.

Inventor： Carl A. Waldspurger ,  Nohhyun Park

IPC: G06F12/08

CPC classification number: G06F12/1063 ,  G06F11/3447 ,  G06F11/3457 ,  G06F12/0802 ,  G06F12/109 ,  G06F12/123 ,  G06F17/5022 ,  G06F2201/885 ,  G06F2212/1021 ,  G06F2212/152 ,  G06F2212/601 ,  G06F2212/6042 ,  G06F2212/684

Abstract: Cache utility curves are determined for different software entities depending on how frequently their storage access requests lead to cache hits or cache misses. Although possible, not all access requests need be tested, but rather only a subset, determined by whether a hash value of each current storage location identifier (such as an address or block number) meets one or more sampling criteria.

Abstract translation: 根据存储访问请求导致缓存命中或高速缓存未命中的频率，为不同的软件实体确定高速缓存实用程序曲线。 虽然可能，但并不是所有的访问请求都需要被测试，而只是一个子集，由每个当前的存储位置标识符（例如地址或块号）的哈希值是否满足一个或多个采样标准来确定。

公开(公告)号：US20140258586A1

公开(公告)日：2014-09-11

申请号：US13785877

申请日：2013-03-05

Applicant: QUALCOMM INCORPORATED

Inventor： Thomas Zeng ,  Azzedine Touzni ,  Tzung Ren Tzeng ,  Phil J. Bostley

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F9/45533 ,  G06F9/45545 ,  G06F9/45558 ,  G06F12/10 ,  G06F2212/151 ,  G06F2212/171 ,  G06F2212/507 ,  G06F2212/654 ,  G06F2212/684

Abstract: A computer system and a method are provided that reduce the amount of time and computing resources that are required to perform a hardware table walk (HWTW) in the event that a translation lookaside buffer (TLB) miss occurs. If a TLB miss occurs when performing a stage 2 (S2) HWTW to find the PA at which a stage 1 (S1) page table is stored, the MMU uses the IPA to predict the corresponding PA, thereby avoiding the need to perform any of the S2 table lookups. This greatly reduces the number of lookups that need to be performed when performing these types of HWTW read transactions, which greatly reduces processing overhead and performance penalties associated with performing these types of transactions.

Abstract translation: 提供一种计算机系统和方法，其在发生翻译后备缓冲器（TLB）未命中的情况下减少执行硬件表行走（HWTW）所需的时间量和计算资源。 如果执行阶段2（S2）HWTW以找到存储第1（S1）页表的PA时发生TLB未命中，则MMU使用IPA预测相应的PA，从而避免执行任何 S2表查找。 这大大减少了执行这些类型的HWTW读取事务时需要执行的查找次数，这大大降低了与执行这些类型的事务相关联的处理开销和性能损失。

公开(公告)号：US08806172B2

公开(公告)日：2014-08-12

申请号：US13843601

申请日：2013-03-15

Applicant: Intel Corporation

Inventor： Jason W. Brandt ,  Sanjoy K. Mondal ,  Richard A. Uhlig ,  Gilbert Neiger ,  Robert T. George

IPC: G06F12/10

CPC classification number: G06F12/1036 ,  G06F9/45533 ,  G06F9/45558 ,  G06F9/4843 ,  G06F12/0292 ,  G06F12/0804 ,  G06F12/0891 ,  G06F12/1027 ,  G06F12/1063 ,  G06F12/109 ,  G06F12/12 ,  G06F12/123 ,  G06F2009/45583 ,  G06F2009/45591 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/30 ,  G06F2212/50 ,  G06F2212/604 ,  G06F2212/657 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684 ,  G06F2212/69 ,  G06F2212/70

Abstract: In one embodiment of the present invention, a method includes switching between a first address space and a second address space, determining if the second address space exists in a list of address spaces; and maintaining entries of the first address space in a translation buffer after the switching. In such manner, overhead associated with such a context switch may be reduced.

Abstract translation: 在本发明的一个实施例中，一种方法包括在第一地址空间和第二地址空间之间切换，确定地址空间列表中是否存在第二地址空间; 并且在切换之后保持翻译缓冲器中的第一地址空间的条目。 以这种方式，可以减少与这种上下文切换相关联的开销。

公开(公告)号：US20140181460A1

公开(公告)日：2014-06-26

申请号：US13723379

申请日：2012-12-21

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lisa Hsu ,  Nuwan Jayasena ,  Andrew Kegel ,  Bradford M. Beckmann

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/1081 ,  G06F2212/302 ,  G06F2212/681 ,  G06F2212/684

Abstract: A data processing device is provided that employs multiple translation look-aside buffers (TLBs) associated with respective processors that are configured to store selected address translations of a page table of a memory shared by the processors. The processing device is configured such that when an address translation is requested by a processor and is not found in the TLB associated with that processor, another TLB is probed for the requested address translation. The probe across to the other TLB may occur in advance of a walk of the page table for the requested address or alternatively a walk can be initiated concurrently with the probe. Where the probe successfully finds the requested address translation, the page table walk can be avoided or discontinued.

Abstract translation: 提供了一种数据处理设备，其采用与相应处理器相关联的多个翻译后备缓冲器（TLB），其配置为存储由处理器共享的存储器的页表的所选地址转换。 处理装置被配置为使得当处理器请求地址转换并且在与该处理器相关联的TLB中没有找到地址转换时，探测另一TLB用于请求的地址转换。 跨越其他TLB的探针可以在针对所请求的地址的页表的行进之前发生，或者可以与探针同时启动步行。 探头成功找到所请求的地址转换的地方，可以避免或停止页表的移动。

公开(公告)号：US20140143498A1

公开(公告)日：2014-05-22

申请号：US13945620

申请日：2013-07-18

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Lena E. Olson ,  Yasuko Eckert ,  Vilas K. Sridharan ,  James M. O'Connor ,  Mark D. Hill ,  Srilatha Manne

IPC: G06F12/08

CPC classification number: G06F12/0802 ,  G06F12/08 ,  G06F12/0804 ,  G06F12/0811 ,  G06F12/0815 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0875 ,  G06F12/1036 ,  G06F12/123 ,  G06F2212/1016 ,  G06F2212/1028 ,  G06F2212/451 ,  G06F2212/6032 ,  G06F2212/683 ,  G06F2212/684 ,  Y02B60/1225 ,  Y02D10/13

Abstract: A method of storing stack data in a cache hierarchy is provided. The cache hierarchy comprises a data cache and a stack filter cache. Responsive to a request to access a stack data block, the method stores the stack data block in the stack filter cache, wherein the stack filter cache is configured to store any requested stack data block.

Abstract translation: 提供了将堆栈数据存储在高速缓存层级中的方法。 缓存层级包括数据高速缓存和堆栈过滤器高速缓存。 响应于访问堆栈数据块的请求，该方法将堆栈数据块存储在堆栈过滤器高速缓存中，其中堆叠过滤器高速缓存被配置为存储任何所请求的栈数据块。

公开(公告)号：US20130318323A1

公开(公告)日：2013-11-28

申请号：US13994577

申请日：2012-03-30

Applicant: Eliezer Weissmann ,  Karthikeyan Karthik Vaithianathan ,  Yoav Zach ,  Boris Ginzburg ,  Ronny Ronen

Inventor： Eliezer Weissmann ,  Karthikeyan Karthik Vaithianathan ,  Yoav Zach ,  Boris Ginzburg ,  Ronny Ronen

IPC: G06F12/10

CPC classification number: G06F12/0811 ,  G06F3/0646 ,  G06F3/0662 ,  G06F3/0668 ,  G06F9/3851 ,  G06F9/3881 ,  G06F9/3887 ,  G06F12/0292 ,  G06F12/084 ,  G06F12/0875 ,  G06F12/1009 ,  G06F12/1027 ,  G06F12/1045 ,  G06F12/1072 ,  G06F12/1081 ,  G06F12/1441 ,  G06F12/145 ,  G06F2212/1024 ,  G06F2212/283 ,  G06F2212/302 ,  G06F2212/452 ,  G06F2212/60 ,  G06F2212/62 ,  G06F2212/65 ,  G06F2212/68 ,  G06F2212/683 ,  G06F2212/684

Abstract: An apparatus and method are described for coupling a front end core to an accelerator component (e.g., such as a graphics accelerator). For example, an apparatus is described comprising: an accelerator comprising one or more execution units (EUs) to execute a specified set of instructions; and a front end core comprising a translation lookaside buffer (TLB) communicatively coupled to the accelerator and providing memory access services to the accelerator, the memory access services including performing TLB lookup operations to map virtual to physical addresses on behalf of the accelerator and in response to the accelerator requiring access to a system memory.

Abstract translation: 描述了用于将前端芯件耦合到加速器部件（例如，诸如图形加速器）的装置和方法。 例如，描述了一种装置，包括：加速器，包括执行指定的一组指令的一个或多个执行单元（EU） 和包括通信地耦合到加速器并且向加速器提供存储器访问服务的翻译后备缓冲器（TLB）的前端核心，所述存储器访问服务包括执行TLB查找操作以代表加速器映射虚拟到物理地址并作为响应 到需要访问系统存储器的加速器。

公开(公告)号：US20130262817A1

公开(公告)日：2013-10-03

申请号：US13432381

申请日：2012-03-28

Applicant: Anthony J. Bybell ,  Michael K. Gschwind

Inventor： Anthony J. Bybell ,  Michael K. Gschwind

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/0292 ,  G06F12/1018 ,  G06F12/1036 ,  G06F2212/1016 ,  G06F2212/651 ,  G06F2212/684

Abstract: Embodiments of the invention relate to hybrid address translation. An aspect of the invention includes receiving a first address, the first address referencing a location in a first address space. The computer searches a segment lookaside buffer (SLB) for a SLB entry corresponding to the first address; the SLB entry comprising a type field and an address field and determines whether a value of the type field in the SLB entry indicates a hashed page table (HPT) search or a radix tree search. Based on determining that the value of the type field indicates the HPT search, a HPT is searched to determine a second address, the second address comprising a translation of the first address into a second address space; and based on determining that the value of the type field indicates the radix tree search, a radix tree is searched to determine the second address.

Abstract translation: 本发明的实施例涉及混合地址转换。 本发明的一个方面包括接收第一地址，第一地址引用第一地址空间中的位置。 计算机搜索段后备缓冲器（SLB）用于对应于第一地址的SLB条目; SLB条目包括类型字段和地址字段，并且确定SLB条目中的类型字段的值是否指示散列页表（HPT）搜索或基数树搜索。 基于确定类型字段的值指示HPT搜索，搜索HPT以确定第二地址，第二地址包括将第一地址转换为第二地址空间; 并且基于确定类型字段的值指示基数树搜索，搜索基数树以确定第二地址。