公开(公告)号：US20240304440A1

公开(公告)日：2024-09-12

申请号：US18468554

申请日：2023-09-15

申请人： Fabric8Labs, Inc.

发明人： Ryan Nicholl ,  David Pain ,  Andrew Edmonds ,  Kareemullah Shaik ,  Edward White

IPC分类号： H01L21/02 ,  H01L21/311 ,  H01L21/48 ,  H01L21/67 ,  H01L21/683

CPC分类号： H01L21/02274 ,  H01L21/02532 ,  H01L21/31116 ,  H01L21/486 ,  H01L21/67063 ,  H01L21/67253 ,  H01L21/6835 ,  B33Y10/00

摘要： Described herein are protected electrode arrays and methods of fabricating thereof. Such electrode arrays can be used in electrochemical-additive manufacturing (ECAM) systems and other systems/applications. In some examples, a protected electrode array comprises an electrode-interface circuit and an interposer bonded to the circuit, e.g., using an adhesive layer. The interposer can include an interposer base formed from silicon, glass, and other like materials suitable for operating environments. The interposer base comprises vias, which are aligned with the circuit's electrode connectors, and interposer electrodes deposited within these vias and electrically coupled to the electrode connectors. In some examples, the interposer comprises a base cover and/or electrode covers positioned over the interposer base and the interposer electrodes, respectively. The interposer can be bonded to the electrode-interface circuit before forming the vias, after forming the vias but before depositing the interposer electrodes, or after depositing the interposer electrodes within the vias.

公开(公告)号：US12089403B2

公开(公告)日：2024-09-10

申请号：US17590266

申请日：2022-02-01

申请人： Lodestar Licensing Group LLC

发明人： M. Jared Barclay ,  Merri L. Carlson ,  Saurabh Keshav ,  George Matamis ,  Young Joon Moon ,  Kunal R. Parekh ,  Paolo Tessariol ,  Vinayak Shamanna

IPC分类号： H10B41/27 ,  H01L21/311 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

CPC分类号： H10B41/27 ,  H01L21/31144 ,  H10B41/10 ,  H10B43/10 ,  H10B43/27

摘要： A method used in forming a memory array comprising strings of memory cells comprises forming a construction comprising a stack that have vertically-alternating insulative tiers and wordline tiers. An array of openings is formed in an uppermost portion of upper material that is above the stack, and the openings comprise channel openings and dummy openings. At least the uppermost portion of the upper material is used as a mask while etching the channel openings and the dummy openings into a lower portion of the upper material. The channel openings are etched into the insulative and wordline tiers. The channel openings are etched deeper into the construction than the dummy openings, and channel material is formed in the channel openings after the etching. Structures independent of method are disclosed.

公开(公告)号：US12087834B2

公开(公告)日：2024-09-10

申请号：US17686978

申请日：2022-03-04

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Shih-Wen Huang ,  Chung-Ting Ko ,  Hong-Hsien Ke ,  Chia-Hui Lin ,  Tai-Chun Huang

IPC分类号： H01L29/417 ,  H01L21/02 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/08 ,  H01L29/45 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L29/41791 ,  H01L21/02063 ,  H01L21/0217 ,  H01L21/02321 ,  H01L21/0234 ,  H01L21/02343 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/3115 ,  H01L21/76802 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/823431 ,  H01L21/823475 ,  H01L29/0847 ,  H01L29/41766 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/7848

摘要： A semiconductor structure is provided. The semiconductor structure includes a gate structure, a source/drain structure, a barrier layer, and a glue layer. The gate structure is over a fin structure. The source/drain structure is in the fin structure and adjacent to the gate structure. The barrier layer is over the source/drain structure. The glue layer is adjacent to the barrier layer. The glue layer has an extending portion in direct contact with the gate structure.

公开(公告)号：US12087707B2

公开(公告)日：2024-09-10

申请号：US17443138

申请日：2021-07-21

申请人： COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES

发明人： Nicolas Posseme ,  Stefan Landis

IPC分类号： H01L23/00 ,  H01L21/311 ,  H01L21/768 ,  H01L23/522

CPC分类号： H01L23/573 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/76877 ,  H01L23/5226

摘要： A method for making an individualization zone of a microchip comprising a first level and a second level of electrical tracks, and a level of interconnections comprising vias. The method includes: providing the first level and a dielectric layer, making a hard metal mask on the dielectric layer, etching the dielectric layer through the mask openings by etching based on fluorinated chemistry, preferably oxidizing the hard metal mask by hydrolysis so as to form randomly distributed residues at certain openings, and filling the openings so as to form at least the vias of the level of interconnections, the vias comprising functional vias at the openings without residues and inactive vias at the openings with residues.

公开(公告)号：US12087593B2

公开(公告)日：2024-09-10

申请号：US17806944

申请日：2022-06-15

申请人： NANYA TECHNOLOGY CORPORATION

发明人： Shih Pin Kuo

IPC分类号： H01L21/311 ,  H01L21/02 ,  H01L21/67

CPC分类号： H01L21/31116 ,  H01L21/0212 ,  H01L21/0217 ,  H01L21/6708

摘要： The present disclosure provides a method of plasma etching including the following operations. A wafer and a nitride layer disposed on the wafer are received. An annular conduit is disposed above an edge portion of the nitride layer, in which the annular conduit has a plurality of holes facing the edge portion of the nitride layer. A plasma is sprayed onto an upper surface of the nitride layer. An unsaturated fluorocarbon is sprayed from the holes of the annular conduit to the edge portion of the nitride layer.

公开(公告)号：US12080779B2

公开(公告)日：2024-09-03

申请号：US17408985

申请日：2021-08-23

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chin-Hsiang Lin ,  Teng-Chun Tsai ,  Huang-Lin Chao ,  Akira Mineji

IPC分类号： H01L29/66 ,  H01L21/311 ,  H01L21/321 ,  H01L29/45 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L29/66515 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/3212 ,  H01L29/45 ,  H01L29/4983 ,  H01L29/66795 ,  H01L29/7851

摘要： The present disclosure describes a method for forming a hard mask on a transistor's gate structure that minimizes gate spacer loss and gate height loss during the formation of self-aligned contact openings. The method includes forming spacers on sidewalls of spaced apart gate structures and disposing a dielectric layer between the gate structures. The method also includes etching top surfaces of the gate structures and top surfaces of the spacers with respect to a top surface of the dielectric layer. Additionally, the method includes depositing a hard mask layer having a metal containing dielectric layer over the etched top surfaces of the gate structures and the spacers and etching the dielectric layer with an etching chemistry to form contact openings between the spacers, where the hard mask layer has a lower etch rate than the spacers when exposed to the etching chemistry.

公开(公告)号：US12080609B2

公开(公告)日：2024-09-03

申请号：US17100944

申请日：2020-11-23

申请人： Taiwan Semiconductor Manufacturing Company, Ltd.

发明人： Hung-Jui Kuo ,  Hui-Jung Tsai ,  Chih Wang

IPC分类号： H01L21/66 ,  G01N27/00 ,  H01L21/02 ,  H01L21/027 ,  H01L21/033 ,  H01L21/311

CPC分类号： H01L22/12 ,  G01N27/00 ,  H01L21/02063 ,  H01L21/02071 ,  H01L21/0274 ,  H01L21/0337 ,  H01L21/31138 ,  H01L21/02057

摘要： Provided is a method of detecting photoresist scums and photoresist residues. A carrier is provided. The carrier has a photoresist layer with opening patterns therein. A plasma etching process is performed to the opening patterns of the photoresist layer. Charges are injected to the opening patterns of the photoresist layer. Whether a photoresist scum or residue is present in at least one of the opening patterns is detected.

公开(公告)号：US12080602B2

公开(公告)日：2024-09-03

申请号：US18331326

申请日：2023-06-08

申请人： Taiwan Semiconductor Manufacturing Company., Ltd.

发明人： Wen-Chun Keng ,  Yu-Kuan Lin ,  Chang-Ta Yang ,  Ping-Wei Wang

IPC分类号： H01L21/8234 ,  H01L27/088 ,  H01L21/3065 ,  H01L21/311 ,  H01L29/08

CPC分类号： H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L27/0886 ,  H01L21/3065 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/0847

摘要： A semiconductor device structure is provided. The semiconductor device structure includes a substrate and a first fin structure and a second fin structure over the substrate. A top surface of the first fin structure and a top surface of the second fin structure are at different height levels. The semiconductor device structure also includes a first semiconductor element on the first fin structure and a second semiconductor element on the second fin structure. The first semiconductor element is wider than the second semiconductor element, and the first semiconductor element is closer to the substrate than the second semiconductor element.

公开(公告)号：US12080597B2

公开(公告)日：2024-09-03

申请号：US17402157

申请日：2021-08-13

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Te-Chih Hsiung ,  Jyun-De Wu ,  Peng Wang ,  Huan-Just Lin

IPC分类号： H01L21/768 ,  H01L21/02 ,  H01L21/311 ,  H01L23/535 ,  H01L29/40 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78

CPC分类号： H01L21/76895 ,  H01L21/02252 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/76805 ,  H01L21/76829 ,  H01L23/535 ,  H01L29/401 ,  H01L29/41791 ,  H01L29/66795 ,  H01L29/7851

摘要： Semiconductor devices and methods of manufacturing the semiconductor devices are described herein. A method includes forming a first etch stop layer from a portion of a gate mask, the gate mask extending between spacers adjacent a gate electrode, the gate electrode overlying a semiconductor fin. The method further includes forming a second etch stop layer adjacent the first etch stop layer, forming an opening through the second etch stop layer, and exposing the first etch stop layer by performing a first etching process. The method further includes extending the opening through the first etch stop layer and exposing the gate electrode by performing a second etching process. Once the gate electrode has been exposed, the method further includes forming a gate contact in the opening.

公开(公告)号：US12080588B2

公开(公告)日：2024-09-03

申请号：US18358321

申请日：2023-07-25

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Lei-Chun Chou ,  Chih-Liang Chen ,  Jiann-Tyng Tzeng ,  Chih-Ming Lai ,  Ru-Gun Liu ,  Charles Chew-Yuen Young

IPC分类号： H01L21/74 ,  H01L23/535 ,  H01L29/66 ,  H01L21/308 ,  H01L21/311 ,  H01L21/3115 ,  H01L21/762 ,  H01L29/78 ,  H10B10/00

CPC分类号： H01L21/743 ,  H01L23/535 ,  H01L29/66795 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31155 ,  H01L21/76224 ,  H01L29/785 ,  H10B10/12

摘要： A semiconductor device includes a buried metal line disposed in a semiconductor substrate, a first dielectric material on a first sidewall of the buried metal line and a second dielectric material on a second sidewall of the buried metal line, a first multiple fins disposed proximate the first sidewall of the buried metal line, a second multiple fins disposed proximate the second sidewall of the buried metal line, a first metal gate structure over the first multiple fins and over the buried metal line, wherein the first metal gate structure extends through the first dielectric material to contact the buried metal line, and a second metal gate structure over the second multiple fins and over the buried metal line.