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公开(公告)号：US20240274534A1
公开(公告)日：2024-08-15
申请号：US18622992
申请日：2024-03-31
申请人： Monolithic 3D Inc.
发明人： Zvi Or-Bach , Jin-Woo Han
IPC分类号： H01L23/528 , G11C16/04 , H01L23/522 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H01L23/5283 , G11C16/0483 , H01L23/5226 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
摘要： A method of making a 3D multilayer semiconductor device, the method comprising: providing a first substrate comprising a first level, said first level comprising a first single crystal silicon layer; providing a second substrate comprising a second level, said second level comprising a second single crystal silicon layer; performing an epitaxial growth of a SiGe layer on top of said second single crystal silicon layer; performing an epitaxial growth of a third single crystal silicon layer on top of said SiGe layer; forming a plurality of second transistors each comprising a single crystal channel; forming a plurality of metal layers interconnecting said plurality of second transistors; and then performing a bonding of said second level onto said first level, wherein performing said bonding comprises making oxide-to-oxide bond zones, and performing removal of a majority of said second single crystal silicon layer.
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32.发明公开公开(公告)号：US20240274198A1
公开(公告)日：2024-08-15
申请号：US18643554
申请日：2024-04-23
IPC分类号： G11C16/04 , H01L29/161 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： G11C16/0483 , H01L29/161 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/10 , H10B43/27 , H10B43/35
摘要： A memory array comprising laterally-spaced memory blocks individually comprises a vertical stack comprising alternating insulative tiers and conductive tiers. Channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. The laterally-spaced memory blocks in a lower one of the conductive tiers comprises elemental-form metal that extends longitudinally-along the laterally-spaced memory blocks proximate laterally -outer sides of the laterally-spaced memory blocks. A metal silicide or a metal-germanium compound is directly against laterally-inner sides of the elemental-form metal in the lower conductive tier and that extends longitudinally-along the laterally-spaced memory blocks in the lower conductive tier. The metal of the metal silicide or of the metal-germanium compound is the same as that of the elemental-form metal. Other embodiments, including method, are disclosed.
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33.发明授权公开(公告)号：US12063778B2
公开(公告)日：2024-08-13
申请号：US17661781
申请日：2022-05-03
IPC分类号： H10B41/27 , H01L21/768 , H10B41/10 , H10B41/35 , H10B41/50 , H10B43/10 , H10B43/27 , H10B43/35
CPC分类号： H10B41/27 , H01L21/76801 , H10B41/10 , H10B41/35 , H10B41/50 , H10B43/10 , H10B43/27 , H10B43/35
摘要： A microelectronic device comprises a stack structure comprising a stack structure comprising alternating conductive structures and insulating structures arranged in tiers, each of the tiers individually comprising one of the conductive structures and one of the insulating structures, staircase structures within the stack structure and having steps comprising edges of the tiers, and a doped dielectric material adjacent the steps of the staircase structures and comprising silicon dioxide doped with one or more of boron, phosphorus, carbon, and fluorine, the doped dielectric material having a greater ratio of Si—O—Si bonds to water than borophosphosilicate glass. Related methods of forming a microelectronic device and related electronic systems are also disclosed.
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公开(公告)号：US12058856B2
公开(公告)日：2024-08-06
申请号：US18231427
申请日：2023-08-08
发明人： Wei Cheng Wu , Li-Feng Teng
IPC分类号： H10B41/42 , H01L21/28 , H01L29/423 , H01L29/66 , H10B41/30 , H10B41/35 , H10B41/44 , H10B41/47 , H10B41/48 , H10B43/30
CPC分类号： H10B41/42 , H01L29/40114 , H01L29/42328 , H01L29/42344 , H01L29/66545 , H10B41/30 , H10B41/35 , H10B41/44 , H10B41/47 , H10B41/48 , H10B43/30
摘要： A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
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公开(公告)号：US20240260270A1
公开(公告)日：2024-08-01
申请号：US18508530
申请日：2023-11-14
发明人： Taeyoon HONG , Janggn YUN , Hyunho KIM , Jeehoon HAN
摘要： A field effect transistor includes a horizontal channel layer, an interlayer insulating layer on the horizontal channel layer, a gate electrode layer on the interlayer insulating layer, a first vertical channel structure passing through the gate electrode layer and the interlayer insulating layer in a vertical direction, in contact with the horizontal channel layer, and connected to one of a source terminal or a drain terminal, and a second vertical channel structure apart from the first vertical channel structure in a horizontal direction, passing through the gate electrode layer and the interlayer insulating layer in the vertical direction, in contact with the horizontal channel layer, and connected to another of the source terminal or the drain terminal.
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公开(公告)号：US20240258401A1
公开(公告)日：2024-08-01
申请号：US18420264
申请日：2024-01-23
申请人： Kioxia Corporation
CPC分类号： H01L29/513 , H01L29/517 , H10B41/27 , H10B41/35 , H10B43/27 , H10B43/35
摘要： A semiconductor device of embodiments includes: a semiconductor layer; a gate electrode layer including a first conductive layer containing a first material and a second conductive layer between the first conductive layer and the semiconductor layer and containing a second material different from the first material; and a first insulating layer between the semiconductor layer and the gate electrode layer and containing aluminum oxide, the aluminum oxide including α (alpha)-aluminum oxide or θ (theta)-aluminum oxide. The direction of the crystal axis of the aluminum oxide falls within a range of ±10° with respect to a first direction from the semiconductor layer toward the gate electrode layer. The direction of the crystal axis of the first material falls within a range of ±10° with respect to the first direction. The direction of the crystal axis of the second material falls within a range of ±10° with respect to the first direction.
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公开(公告)号：US20240251554A1
公开(公告)日：2024-07-25
申请号：US18584275
申请日：2024-02-22
摘要： Some embodiments include an integrated assembly having a memory region and another region adjacent the memory region. Channel-material-pillars are arranged within the memory region, and conductive posts are arranged within said other region. A source structure is coupled to lower regions of the channel-material-pillars. A panel extends across the memory region and the other region. Doped-semiconductor-material is directly adjacent to the panel within the memory region and the other region. The doped-semiconductor-material is at least part of the source structure within the memory region. Liners are directly adjacent to the conductive posts and laterally surround the conductive posts. The liners are between the conductive posts and the doped-semiconductor-material. Some embodiments include methods of forming integrated assemblies.
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公开(公告)号：US20240251553A1
公开(公告)日：2024-07-25
申请号：US18493122
申请日：2023-10-24
发明人： Young Bong SHIN , Ji Hoon LEE , Mi Hye KANG , Jun Hee NA , Phil Ouk NAM , Tae Gi YEH
IPC分类号： H10B43/27 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
CPC分类号： H10B43/27 , H10B41/10 , H10B41/27 , H10B41/35 , H10B41/40 , H10B43/10 , H10B43/35 , H10B43/40
摘要： A semiconductor memory device includes a stack structure on a substrate, extending in a first direction, and including gate electrode layers and insulating layers stacked alternately with each other, a vertical structure including a vertical channel film extending in a second direction crossing the first direction and a channel insulating film disposed on the vertical channel film and having first areas adjacent to the insulating layers and second areas adjacent to the gate electrode layers, and a high-k film on the channel insulating film. The high-k film includes a first high-k metal oxide film between the first areas and the insulating layers and in contact with the first areas and a second high-k metal oxide film between the second areas and the gate electrode layers and in contact with the second areas, and the first and second high-k metal oxide films include different metal materials.
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公开(公告)号：US12046512B2
公开(公告)日：2024-07-23
申请号：US17464439
申请日：2021-09-01
申请人： SK hynix Inc.
发明人： Nam Jae Lee
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528 , H01L29/78 , H10B41/27 , H10B41/35 , H10B41/50 , H10B43/27 , H10B43/35
CPC分类号： H01L21/76897 , H01L21/76816 , H01L23/5226 , H01L23/528 , H01L29/78 , H10B41/27 , H10B41/35 , H10B41/50 , H10B43/27 , H10B43/35
摘要： A semiconductor device may comprise a plurality of conductive lines and a plurality of contact plugs. The plurality of conductive lines may include a first conductive line a second conductive line. The plurality of contact plugs may include a first contact plug and a second contact plug. The first contact plug may have a first pillar portion and a first protruding portion protruding from a sidewall of the first pillar portion at a first depth, so as to be in alignment and contact with a sidewall of the first conductive line. The second contact plug may have a second pillar portion and a second protruding portion protruding from a sidewall of the second pillar portion at a second depth, so as to be in alignment and contact with a sidewall of the second conductive line.
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公开(公告)号：US20240237351A1
公开(公告)日：2024-07-11
申请号：US18581049
申请日：2024-02-19
发明人： Taisoo Lim , Suhyeong Lee
IPC分类号： H10B43/27 , H01L29/423 , H01L29/788 , H01L29/792 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/35
CPC分类号： H10B43/27 , H01L29/42324 , H01L29/4234 , H01L29/7889 , H01L29/7926 , H10B41/10 , H10B41/27 , H10B41/35 , H10B43/35
摘要： Semiconductor devices are provided. A semiconductor device includes gate electrodes on a substrate and stacked perpendicularly to an upper surface of the substrate. The semiconductor device includes interlayer insulating layers alternately stacked with the gate electrodes. Moreover, the semiconductor device includes channel structures passing through the gate electrodes. Each of the channel structures includes a channel layer extending perpendicularly to the upper surface of the substrate, a tunneling insulating layer on the channel layer, charge storage layers on the tunneling insulating layer in respective regions between the gate electrodes and a side surface of the tunneling insulating layer, and first blocking insulating layers on the charge storage layers, respectively. A first layer of the first blocking insulating layers is on an upper surface, a lower surface, and a side surface of a first layer of the charge storage layers.
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