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    Memory signal buffers and modules supporting variable access granularity
    391.
    发明授权
    Memory signal buffers and modules supporting variable access granularity 有权
    内存信号缓冲区和支持可变访问粒度的模块

    公开(公告)号：US09268719B2

    公开(公告)日：2016-02-23

    申请号：US13566417

    申请日：2012-08-03

    Applicant: Ian Shaeffer

    Inventor： Ian Shaeffer

    IPC: G06F3/00 ,  G06F13/00 ,  G06F13/16

    CPC classification number: G11C7/1048 ,  G06F12/1009 ,  G06F12/1027 ,  G06F13/16 ,  G06F13/1673 ,  G06F2212/657 ,  G06F2212/68 ,  G11C7/1072 ,  Y02D10/14

    Abstract: Described are memory modules that include a configurable signal buffer that manages communication between memory devices and a memory controller. The buffer can be configured to support threading to reduce access granularity, the frequency of row-activation, or both. The buffer can translate controller commands to access information of a specified granularity into subcommands seeking to access information of reduced granularity. The reduced-granularity information can then be combined, as by concatenation, and conveyed to the memory controller as information of the specified granularity.

    Abstract translation: 描述的是包括管理存储器设备和存储器控制器之间的通信的可配置信号缓冲器的存储器模块。 缓冲区可以配置为支持线程以减少访问粒度，行激活的频率，或两者兼而有之。 缓冲区可以转换控制器命令以将指定粒度的信息访问寻求访问降低粒度的信息的子命令。 然后可以通过连接将小粒度信息组合起来，并将其作为指定粒度的信息传送到存储器控制器。

    System and module comprising an electrically erasable programmable memory chip
    392.
    发明授权
    System and module comprising an electrically erasable programmable memory chip 有权
    包括电可擦除可编程存储器芯片的系统和模块

    公开(公告)号：US09262269B2

    公开(公告)日：2016-02-16

    申请号：US14836467

    申请日：2015-08-26

    Applicant: Rambus Inc.

    Inventor： Yuanlong Wang ,  Frederick A. Ware

    IPC: G11C29/00 ,  G06F11/00 ,  G06F11/14 ,  H03M13/29 ,  G06F11/10

    CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

    Abstract: A controller includes a link interface that is to couple to a first link to communicate bi-directional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

    Abstract translation: 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

    Memory device with retransmission upon error
    393.
    发明授权
    Memory device with retransmission upon error 有权
    存储设备错误重传

    公开(公告)号：US09262262B2

    公开(公告)日：2016-02-16

    申请号：US14853869

    申请日：2015-09-14

    Applicant: Rambus Inc.

    Inventor： Yuanlong Wang ,  Frederick A. Ware

    IPC: H03M13/00 ,  G06F11/10 ,  H03M13/09

    CPC classification number: G06F11/0727 ,  G06F3/0619 ,  G06F3/064 ,  G06F3/0679 ,  G06F11/073 ,  G06F11/0751 ,  G06F11/076 ,  G06F11/0793 ,  G06F11/10 ,  G06F11/1004 ,  G06F11/1008 ,  G06F11/1044 ,  G06F11/1068 ,  G06F11/1402 ,  G06F13/4286 ,  H03M13/09 ,  H03M13/29 ,  H03M13/2906 ,  H03M13/611 ,  H04L1/0003 ,  H04L1/0008 ,  H04L1/0061 ,  H04L1/08 ,  H04L1/1867 ,  H04L2001/0093

    Abstract: A controller includes a link interface that is to couple to a first link to communicate bidirectional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.

    Abstract translation: 控制器包括要耦合到第一链路以传送双向数据的链路接口和用于发送单向错误检测信息的第二链路。 编码器将动态地将第一错误检测信息添加到写入数据的至少一部分。 耦合到链路接口的发射机是发送写入数据。 延迟元件耦合到编码器的输出。 耦合到链路接口的接收机是接收对应于写数据的至少一部分的第二错误检测信息。 错误检测逻辑耦合到来自延迟元件的输出和来自接收器的输出。 错误检测逻辑是通过比较第一错误检测信息和第二错误检测信息来确定写入数据的至少一部分中的错误，并且如果检测到错误则是断言错误状况。

    Memory controller with clock-to-strobe skew compensation
    394.
    发明授权
    Memory controller with clock-to-strobe skew compensation 有权

    公开(公告)号：US09229470B2

    公开(公告)日：2016-01-05

    申请号：US14267446

    申请日：2014-05-01

    Applicant: Rambus Inc.

    Inventor： Frederick A. Ware

    IPC: G11C7/10 ,  G06F12/00 ,  G06F1/10 ,  G11C7/22 ,  G06F13/16 ,  G06F13/42 ,  G11C8/18

    CPC classification number: G11C11/4076 ,  G06F1/10 ,  G06F13/1689 ,  G06F13/4243 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/18 ,  G11C11/409 ,  G11C2207/2254

    Abstract: A clock signal is transmitted to first and second integrated circuit (IC) components via a clock signal line, the clock signal having a first arrival time at the first IC component and a second, later arrival time at the second IC component. A write command is transmitted to the first and second IC components to be sampled by those components at respective times corresponding to transitions of the clock signal, and write data is transmitted to the first and second IC components in association with the write command. First and second strobe signals are transmitted to the first and second IC components, respectively, to time reception of the first and second write data in those components. The first and second strobe signals are selected from a plurality of phase-offset timing signals to compensate for respective timing skews between the clock signal and the first and second strobe signals.

    Memory controller with fast reacquisition of read timing to support rank switching
    395.
    发明授权
    Memory controller with fast reacquisition of read timing to support rank switching 有权
    内存控制器快速重新读取读取时序，以支持等级切换

    公开(公告)号：US09213657B2

    公开(公告)日：2015-12-15

    申请号：US13817135

    申请日：2011-08-04

    Applicant: Jared L. Zerbe ,  Ian Shaeffer

    Inventor： Jared L. Zerbe ,  Ian Shaeffer

    IPC: G11C7/22 ,  G06F13/16 ,  G11C8/18

    CPC classification number: G06F13/1689 ,  G06F2213/0038 ,  G11C7/22 ,  G11C8/18 ,  Y02D10/14

    Abstract: Techniques for performing fast timing reacquisition of read timing in a memory controller to support rank switching device are described. During operation, a memory controller receives read data for a read operation, wherein the read data includes a calibration preamble. The memory controller uses the calibration preamble to perform a fast timing reacquisition operation to compensate for a timing drift between a clock path and a data path for the read data. In particular, the memory controller performs the fast timing reacquisition by adjusting a data delay line coupled to a clock path associated with a control loop, wherein the control loop controls a data clock which is used to receive read data at the memory controller.

    Abstract translation: 描述用于在存储器控制器中执行快速定时重新获取读取定时以支持等级切换装置的技术。 在操作期间，存储器控制器接收用于读取操作的读取数据，其中读取的数据包括校准前导码。 存储器控制器使用校准前导码来执行快速定时重新获取操作以补偿用于读取数据的时钟路径和数据路径之间的定时漂移。 特别地，存储器控制器通过调整耦合到与控制环路相关联的时钟路径的数据延迟线来执行快速定时重新获取，其中控制回路控制用于在存储器控制器处接收读取数据的数据时钟。

    Clock recovery circuit
    396.
    发明授权
    Clock recovery circuit 有权

    公开(公告)号：US09209966B1

    公开(公告)日：2015-12-08

    申请号：US14687766

    申请日：2015-04-15

    Applicant: Rambus Inc.

    Inventor： Masum Hossain ,  Jared L. Zerbe ,  Myeong-Jae Park

    IPC: H03D3/24 ,  H04L7/033 ,  H04L7/00 ,  H04L25/03 ,  H03L7/091

    CPC classification number: H04L7/0331 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/091 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/0337 ,  H04L25/03146 ,  H04L2025/03445

    Abstract: This disclosure provides a clock recovery circuit having a phase-locked loop (PLL) with two-point modulation. A binary phase-error signal controls a variable frequency oscillator's (VFO's) feedback path, while a linear phase-error signal controls the PLL outside of that feedback path. The linear phase-error signal is injected using an ultra-low latency delay path. While the binary phase-error signal sets the lock-point of the PLL, the linear phase-error path dominates at high frequencies and also helps reduce dither jitter. Other optional features include an area-efficient hybrid phase detector that generates both the binary and linear phase-error signals, use of a phase interpolator inside the PLL to further smooth dither jitter, recovered clock update filtering for specific data transitions, and support for multi-PAM signaling.

    Communication channel calibration using feedback
    400.
    发明授权
    Communication channel calibration using feedback 有权

    公开(公告)号：US09172521B2

    公开(公告)日：2015-10-27

    申请号：US13399194

    申请日：2012-02-17

    Applicant: Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

    Inventor： Jun Kim ,  Wayne S. Richardson ,  Glenn Chiu

    IPC: G06F19/00 ,  H04L5/14 ,  H04L25/03

    CPC classification number: H04B17/11 ,  H04L5/1438 ,  H04L25/03343 ,  H04L2025/03802

    Abstract: A method for calibrating a communication channel coupling first and second components includes transmitting a data signal from the first component to the second component on the communication channel, and sensing a characteristic, such as phase, of the data signal on the second component. Information about the sensed characteristic is fed back to the first component using an auxiliary channel. An adjustable parameter, such as phase, for the transmitter is adjusted on the first component in response to the information. Also, a characteristic of a data signal received from the transmitter on the second component is sensed and used to adjust an adjustable parameter for the receiver on the first component.

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