公开(公告)号：US12118230B2

公开(公告)日：2024-10-15

申请号：US18107694

申请日：2023-02-09

Applicant: Micron Technology, Inc.

Inventor： Bryan Hornung ,  Tony M. Brewer

IPC: G06F3/06

CPC classification number: G06F3/0653 ,  G06F3/0607 ,  G06F3/0679

Abstract: Disclosed in some examples are methods, systems, memory devices, and machine-readable mediums that allows an application of a computer system to create a series of one or more logs of writes to one or more memory locations of a memory device. The logs may comprise the values at the end of the log interval of the one or more memory locations that were written to during a log interval. In some examples, the logs do not include intermediate writes to the one or more memory locations (only the final value) and do not include values of memory locations that were not written to during the interval. After an event, software can apply these logs to a copy of the original memory region state to recover the contents of the locations at any of the logged points. These logs may be useful to recreate the state of the memory at various points during the application's execution.

公开(公告)号：US20240339158A1

公开(公告)日：2024-10-10

申请号：US18625800

申请日：2024-04-03

Applicant: Micron Technology, Inc.

Inventor： Sheyang Ning ,  Lawrence Celso Miranda ,  Jeffrey S. McNeil ,  Tomoko Ogura Iwasaki ,  Yeang Meng Hern ,  Lee-eun Yu ,  Albert Fayrushin ,  Fulvio Rori ,  Justin Bates

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10

Abstract: Control logic in a memory device initiates a program operation including a first phase including applying a ramping voltage level to a set of wordlines of a memory device to boost a set of pillar voltages and a second phase including applying a set of programming pulses to a wordline associated with one or more memory cells of the memory device to be programmed to a set of programming levels, wherein each programming level of the set of programming levels is programmed by each programming pulse. During the first phase of the program operation, a first voltage applied to a drain-side select line (SGD) is adjusted from a first SGD voltage level to a second SGD voltage level.

公开(公告)号：US20240339152A1

公开(公告)日：2024-10-10

申请号：US18627960

申请日：2024-04-05

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim ,  Wonjun Choi

IPC: G11C11/4091 ,  G11C11/4078 ,  G11C11/4096

CPC classification number: G11C11/4091 ,  G11C11/4078 ,  G11C11/4096

Abstract: Apparatuses and techniques for implementing a data sense amplifier circuit with a hybrid architecture. With the hybrid architecture, the data sense amplifier circuit includes a first set of amplifiers that are shared by multiple banks and includes a second set of amplifiers with multiple subsets dedicated to different banks. The bank-shared amplifiers support memory operations (e.g., a read operation) across multiple banks. Each amplifier within the first set of amplifiers is coupled to at least two banks. The bank-specific amplifiers support usage-based disturbance mitigation for a corresponding bank. Each amplifier within the second set of amplifiers is coupled to one of the multiple banks. The bank-shared amplifiers enable the data sense amplifier circuit to have a smaller footprint while the bank-specific amplifiers enable the data sense amplifier circuit to support usage-based disturbance mitigation and avoid conflicts associated with some sequences of commands.

公开(公告)号：US20240338139A1

公开(公告)日：2024-10-10

申请号：US18748715

申请日：2024-06-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Wai Leong Chin ,  Francis Chee Khai Chew ,  Trismardawi Tanadi ,  Chun Sum Yeung ,  Lawrence Dumalag ,  Ekamdeep Singh

IPC: G06F3/06 ,  G06F12/06

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0653 ,  G06F3/0679 ,  G06F12/0646 ,  G06F2212/7202 ,  G06F2212/7204 ,  G06F2212/7206

Abstract: A memory sub-system causing execution of a first wordline leakage test of a first wordline group of a set of wordline groups of a memory block in response to determining a temperature of the memory block is within a threshold temperature range. A first result of the first wordline leakage test is determined. A second wordline leakage test of a second wordline group is caused to be executed and a second result is determined. A determination is made that the first result of the first wordline leakage test of the first wordline group satisfies a first condition. A determination is made that the second result of the second wordline leakage test of the second wordline group satisfies a second condition. In response to satisfaction of the conditions, an action is executed.

公开(公告)号：US12114499B2

公开(公告)日：2024-10-08

申请号：US17720223

申请日：2022-04-13

Applicant: Micron Technology, Inc.

Inventor： Aaron S. Yip

IPC: G11C8/10 ,  G11C11/56 ,  G11C16/08 ,  G11C16/24 ,  G11C16/26 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/528 ,  H10B41/27 ,  H10B43/27

CPC classification number: H10B43/27 ,  G11C11/5621 ,  G11C11/5671 ,  G11C16/08 ,  G11C16/24 ,  H01L21/32133 ,  H01L21/76892 ,  H01L23/5283 ,  H10B41/27

Abstract: A memory device stores data in non-volatile memory. The memory device includes a non-volatile memory array. The memory array includes tiers for accessing data stored in blocks of the memory array, including a block having a left block portion and a right block portion. A first staircase is positioned between the left block portion and the right block portion, and a bottom portion of the first staircase includes steps corresponding to first tiers of the left block portion. A second staircase is positioned between the left block portion and the right block portion, and a top portion of the second staircase includes steps corresponding to second tiers of the right block portion. The steps of the first staircase and the steps of the second staircase descend in opposite directions.

公开(公告)号：US12114062B2

公开(公告)日：2024-10-08

申请号：US18368279

申请日：2023-09-14

Applicant: Micron Technology, Inc.

Inventor： Marta Egorova

IPC: H04N23/50 ,  H04N23/60 ,  H04N23/90

CPC classification number: H04N23/64 ,  H04N23/50 ,  H04N23/90

Abstract: Methods and devices related to selecting image sensors are described. In an example, a method can include receiving, at a processing resource of a computing device, first signaling indicative of image data from a plurality of image sensors that are located under a surface of a display of the computing device; receiving, at the processing resource of the computing device, second signaling indicative of display data indicating a first portion of the display is active when the computing device is running an application, determining, at the processing resource, that a first image sensor of the plurality of sensors is closest to the first portion of the display, and selecting the first image sensor of the plurality of sensors closest to the first portion of the display for generating image data for the application.

公开(公告)号：US12113092B2

公开(公告)日：2024-10-08

申请号：US18313638

申请日：2023-05-08

Applicant: Micron Technology, Inc.

Inventor： Vladimir Odnoblyudov ,  Martin F. Schubert

IPC: H01L27/15 ,  H01L23/60 ,  H01L25/16 ,  H01L33/00 ,  H01L33/38 ,  H01L33/40

CPC classification number: H01L27/15 ,  H01L23/60 ,  H01L33/0075 ,  H01L33/0093 ,  H01L33/382 ,  H01L33/405 ,  H01L25/167 ,  H01L2924/0002 ,  H01L2933/0016 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Solid state transducer devices having integrated electrostatic discharge protection and associated systems and methods are disclosed herein. In one embodiment, a solid state transducer device includes a solid state emitter, and an electrostatic discharge device carried by the solid state emitter. In some embodiments, the electrostatic discharge device and the solid state emitter share a common first contact and a common second contact. In further embodiments, the solid state lighting device and the electrostatic discharge device share a common epitaxial substrate. In still further embodiments, the electrostatic discharge device is positioned between the solid state lighting device and a support substrate.

公开(公告)号：US12112828B2

公开(公告)日：2024-10-08

申请号：US17938002

申请日：2022-10-04

Applicant: Micron Technology, Inc.

Inventor： Carl L. Minifie ,  Phong T. Nguyen ,  Alexander A. Tomaso

IPC: G11C7/10 ,  G11C11/4076

CPC classification number: G11C7/109 ,  G11C7/1069 ,  G11C7/1093 ,  G11C11/4076

Abstract: Methods, systems, and devices for modification of a command timing pattern are described. A host device may transmit (e.g., issue), to a memory device, a quantity of deselect commands between activation or data access commands to satisfy configured timing constraints. Each deselect command may indicate a polarity (e.g., a high voltage or a low voltage) for a command and address (CA) pin at the memory device. In some examples, the quantity of deselect commands may include one or more sequences of deselect commands (e.g., low-high-high-high). The host device may truncate a sequence of deselect commands, for example to satisfy timing constraints without transmitting additional unnecessary commands. By dynamically configuring the quantity of deselect commands, the host device may improve latency and overall efficiency of system operations without violating the configured timing constraints.

公开(公告)号：US12112789B2

公开(公告)日：2024-10-08

申请号：US17752553

申请日：2022-05-24

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Takayuki Miyamoto

IPC: G11C16/04 ,  G06F13/16 ,  G11C11/4076 ,  G11C11/4096 ,  H03K19/20

CPC classification number: G11C11/4076 ,  G06F13/1673 ,  G11C11/4096 ,  H03K19/20

Abstract: Apparatuses, systems, and methods for input buffer enable clock synchronization. A command shifter receives a command, such as a write command. The command shifter passes the command through latches of the shifter in synchronization with a clock signal. Data buffer enable logic provides a data buffer enable signal with a level based on how long it takes the command to pass through the command shifter. The data buffer enable logic synchronizes changes to the level of the data buffer enable signal to the clock signal.

公开(公告)号：US12112258B2

公开(公告)日：2024-10-08

申请号：US18131949

申请日：2023-04-07

Applicant: Micron Technology, Inc.

Inventor： Vijay S. Ramesh ,  Richard C. Murphy

IPC: G06N3/065 ,  G06F7/48 ,  G11C11/4063 ,  H03M1/12 ,  H03M1/66

CPC classification number: G06N3/065 ,  G06F7/48 ,  G11C11/4063 ,  H03M1/12 ,  H03M1/66

Abstract: Systems, apparatuses, and methods related to a neuron built with posits are described. An example system may include a memory device and the memory device may include a plurality of memory cells. The plurality of memory cells can store data including a bit string in an analog format. A neuromorphic operation can be performed on the data in the analog format. The example system may include an analog to digital converter coupled to the memory device. The analog to digital converter may convert the bit string in the analog format stored in at least one of the plurality of memory cells to a format that supports arithmetic operations to a particular level of precision.