公开(公告)号：US10014282B2

公开(公告)日：2018-07-03

申请号：US15721955

申请日：2017-10-01

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L21/00 ,  H01L25/065 ,  H01L23/00 ,  H01L25/00 ,  H01L21/74 ,  H01L29/66 ,  H01L27/06 ,  H01L23/485 ,  H01L23/48 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L29/78 ,  H01L29/423 ,  H01L27/092

Abstract: An Integrated Circuit device, the device including: a base wafer including a single crystal layer, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors, where the base wafer includes a memory bit-cell array including the first transistors and control bit-lines and word-lines; and a second layer including a plurality of second transistors, the second layer overlying the at least one metal layer, where the second layer includes a connecting via to the bit-lines or the word-lines, the connecting via has a diameter of less than 200 nm, and where the second layer includes control circuits to control the memory bit-cell array, the control circuits include the second transistors.

公开(公告)号：US09871034B1

公开(公告)日：2018-01-16

申请号：US13731108

申请日：2012-12-30

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L29/80 ,  H01L27/04 ,  H01L27/088

CPC classification number: H01L27/04 ,  H01L27/088

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; and a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, and the second layer overlying the at least one metal layer; wherein the material composition of at least one of the plurality of second single crystal transistors is substantially different than the material composition of at least one of the plurality of first transistors.

公开(公告)号：US09613887B2

公开(公告)日：2017-04-04

申请号：US15079017

申请日：2016-03-23

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L23/48 ,  H01L27/088 ,  H01L23/367 ,  H01L23/522 ,  H01L27/06 ,  H01L21/8234 ,  H01L27/092

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between at least a portion of the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second transistors, the second layer overlying the at least one metal layer; and at least one conductive structure constructed to provide power to a portion of the second transistors, where the provide power is controlled by at least one of the transistors.

公开(公告)号：US09564432B2

公开(公告)日：2017-02-07

申请号：US14509288

申请日：2014-10-08

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Deepak C. Sekar ,  Brian Cronquist ,  Israel Beinglass ,  Jan Lodewijk de Jong

IPC: H01L27/088 ,  G11C17/14 ,  H01L21/762 ,  H01L21/822 ,  H01L21/84 ,  H01L23/525 ,  H01L23/544 ,  H01L25/065 ,  H01L25/18 ,  H01L27/02 ,  H01L27/06 ,  H01L27/092 ,  H01L27/105 ,  H01L27/108 ,  H01L27/11 ,  H01L27/112 ,  H01L27/118 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/177 ,  H01L21/8226 ,  H01L23/48 ,  H01L23/528 ,  H01L23/532 ,  H01L23/00

CPC classification number: H01L27/088 ,  G11C17/14 ,  H01L21/76254 ,  H01L21/8221 ,  H01L21/8226 ,  H01L21/84 ,  H01L23/481 ,  H01L23/5252 ,  H01L23/528 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/544 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L25/0657 ,  H01L25/18 ,  H01L27/0207 ,  H01L27/0688 ,  H01L27/0694 ,  H01L27/092 ,  H01L27/105 ,  H01L27/10873 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/11 ,  H01L27/1108 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/11803 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2224/32145 ,  H01L2224/45124 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/73265 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01066 ,  H01L2924/01322 ,  H01L2924/10253 ,  H01L2924/12032 ,  H01L2924/12036 ,  H01L2924/12042 ,  H01L2924/1301 ,  H01L2924/1305 ,  H01L2924/13062 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/3011 ,  H01L2924/3025 ,  H03K17/687 ,  H03K19/0948 ,  H03K19/177 ,  H01L2924/00 ,  H01L2224/80001 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device, including: a first layer including monocrystalline material and first transistors, the first transistors overlaid by a first isolation layer; a second layer including second transistors and overlaying the first isolation layer, the second transistors including a monocrystalline material; where the second layer includes at least one through layer via to provide connection between at least one of the second transistors and at least one of the first transistors, where the at least one through layer via has a diameter of less than 200 nm; a first set of external connections underlying the first layer to connect the device to external devices; and a second set of external connections overlying the second layer to connect the device to external devices.

Abstract translation: 一种半导体器件，包括：第一层，包括单晶材料和第一晶体管，所述第一晶体管由第一隔离层覆盖; 包括第二晶体管并覆盖第一隔离层的第二层，第二晶体管包括单晶材料; 其中所述第二层包括至少一个贯通层通孔，以在所述第二晶体管中的至少一个与所述第一晶体管中的至少一个之间提供连接，其中所述至少一个贯通层通孔的直径小于200nm; 第一层的第一组外部连接，用于将设备连接到外部设备; 以及覆盖第二层以将设备连接到外部设备的第二组外部连接。

公开(公告)号：US09385058B1

公开(公告)日：2016-07-05

申请号：US13803437

申请日：2013-03-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L21/70 ,  H01L27/12 ,  H01L23/34

CPC classification number: H01L21/4871 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including first electronic circuits and a plurality of first single crystal transistors; at least one metal layer; and a second layer including second electronic circuits and a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; the second layer includes a through layer via with a diameter of less than 150 nm; a portion of the first electronic circuits is circumscribed by a first dice lane, and there are no conductive connections to the portion of the first electronic circuits that cross the first dice lane; wherein a portion of the second electronic circuits is circumscribed by a second dice lane, and there are no conductive connections to the portion of the second electronic circuits that cross the second dice lane, and the second dice lane is overlaying and aligned to the first dice lane.

Abstract translation: 一种集成电路装置，包括：基底晶片，包括第一电子电路和多个第一单晶晶体管; 至少一个金属层; 以及包括第二电子电路和多个第二单晶体晶体管的第二层，所述第二层覆盖所述至少一个金属层; 第二层包括直径小于150nm的贯通层通孔; 第一电子电路的一部分由第一骰子通道限定，并且不与第一电子电路的穿过第一骰子通道的部分的导电连接; 其中所述第二电子电路的一部分由第二骰子通道限定，并且没有与所述第二电子电路的穿过所述第二骰子通道的所述部分的导电连接，并且所述第二骰子通道覆盖并对齐到所述第一骰子 车道。

公开(公告)号：US20150340316A1

公开(公告)日：2015-11-26

申请号：US14814865

申请日：2015-07-31

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/528 ,  H01L27/108 ,  H01L27/115 ,  H01L27/24

CPC classification number: H01L23/528 ,  G11C5/025 ,  G11C5/04 ,  G11C8/16 ,  G11C11/403 ,  G11C13/0007 ,  G11C2213/71 ,  G11C2213/75 ,  H01L27/0688 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/2436 ,  H01L27/2481 ,  H01L27/249 ,  H01L45/04 ,  H01L45/06 ,  H01L45/08 ,  H01L45/085 ,  H01L45/1226 ,  H01L45/141 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L2224/16145 ,  H01L2224/32145

Abstract: A 3D device, including: a first layer including a first memory including a first transistor; and a second layer including a second memory including a second transistor; where the second transistor is self-aligned to the first transistor, and where the first transistor and the second transistor each being a junction-less transistor.

Abstract translation: 一种3D设备，包括：包括第一存储器的第一层，所述第一存储器包括第一晶体管; 以及包括包括第二晶体管的第二存储器的第二层; 其中所述第二晶体管与所述第一晶体管自对准，并且其中所述第一晶体管和所述第二晶体管均为无结型晶体管。

公开(公告)号：US20150311142A1

公开(公告)日：2015-10-29

申请号：US14747599

申请日：2015-06-23

Applicant: Monolithic 3D Inc.

Inventor： Deepak Sekar ,  Zvi Or-Bach ,  Brian Cronquist

IPC: H01L23/48 ,  H01L27/088 ,  H01L23/367

CPC classification number: H01L25/0657 ,  H01L21/823475 ,  H01L23/3677 ,  H01L23/481 ,  H01L23/5225 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/092 ,  H01L27/0922 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D device including: a first layer including first transistors, the first layer overlaid by at least one interconnection layer; a second layer including second transistors, the second layer overlaying the interconnection layer; a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, where the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to a top or bottom surface of the 3D device.

Abstract translation: 一种3D设备，包括：包括第一晶体管的第一层，由至少一个互连层覆盖的第一层; 第二层，包括第二晶体管，第二层覆盖互连层; 将所述第二晶体管与所述互连层连接的多个电连接; 以及至少一个导热和非导电接触，其中所述至少一个导热和非导电接触将所述第二层热连接到所述3D器件的顶表面或底表面。

公开(公告)号：US09117749B1

公开(公告)日：2015-08-25

申请号：US13836080

申请日：2013-03-15

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L27/24 ,  H01L27/108 ,  H01L27/115 ,  H01L27/06

CPC classification number: H01L27/2436 ,  G11C8/16 ,  H01L24/13 ,  H01L24/16 ,  H01L27/0688 ,  H01L27/101 ,  H01L27/10802 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/1108 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11578 ,  H01L27/228 ,  H01L27/2481 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/145 ,  H01L45/146 ,  H01L2224/131 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/13091 ,  H01L2924/1436 ,  H01L2924/1438 ,  H01L2924/014 ,  H01L2924/00

Abstract: A semiconductor device, including: a first transistor sharing a first diffusion with a second transistor; a third transistor sharing a second diffusion with the second transistor; and at least one programmable resistor; wherein the at least one programmable resistor is connected to the first diffusion and the second diffusion, wherein the at least one programmable resistor includes one of the following: memristor, transition metal oxides, polymeric memristor, ferroelectric memristor, spintronic memristor, spin transfer torque, phase-change structure, programmable metallization structure, conductive-bridging structure, magnetoresistive structure, chalcogenide structure.

Abstract translation: 一种半导体器件，包括：与第二晶体管共享第一扩散的第一晶体管; 与所述第二晶体管共享第二扩散的第三晶体管; 和至少一个可编程电阻器; 其中所述至少一个可编程电阻器连接到所述第一扩散层和所述第二扩散层，其中所述至少一个可编程电阻器包括以下之一：忆阻器，过渡金属氧化物，聚合物忆阻器，铁电忆阻器，自旋电子忆阻器， 相变结构，可编程金属化结构，导电桥接结构，磁阻结构，硫族化物结构。

公开(公告)号：US20150069523A1

公开(公告)日：2015-03-12

申请号：US14541452

申请日：2014-11-14

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist

IPC: H01L25/065 ,  H01L23/00 ,  H01L27/088

CPC classification number: H01L25/0657 ,  H01L21/743 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/485 ,  H01L23/522 ,  H01L24/25 ,  H01L25/50 ,  H01L27/0688 ,  H01L27/088 ,  H01L27/092 ,  H01L29/4236 ,  H01L29/66621 ,  H01L29/78 ,  H01L2224/24146 ,  H01L2225/06544 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/01104 ,  H01L2924/12032 ,  H01L2924/12042 ,  H01L2924/13091 ,  H01L2924/2064 ,  H01L2924/351 ,  H01L2924/00

Abstract: An Integrated Circuit device, including: a base wafer including single crystal, the base wafer including a plurality of first transistors; at least one metal layer providing interconnection between the plurality of first transistors; a second layer of less than 2 micron thickness, the second layer including a plurality of second single crystal transistors, the second layer overlying the at least one metal layer; and at least one conductive structure underneath at least one of the second single crystal transistors, the at least one conductive structure is constructed to provide a back-bias to at least one of the second single crystal transistors.

Abstract translation: 一种集成电路器件，包括：包括单晶的基底晶片，所述基底晶片包括多个第一晶体管; 提供所述多个第一晶体管之间的互连的至少一个金属层; 第二层小于2微米厚，第二层包括多个第二单晶晶体管，第二层覆盖至少一个金属层; 以及在所述第二单晶体晶体管中的至少一个下方的至少一个导电结构，所述至少一个导电结构被构造为向所述第二单晶体晶体管中的至少一个提供反偏压。

公开(公告)号：US08803206B1

公开(公告)日：2014-08-12

申请号：US13855786

申请日：2013-04-03

Applicant: Monolithic 3D Inc.

Inventor： Zvi Or-Bach ,  Brian Cronquist ,  Deepak Sekar

IPC: H01L23/60 ,  H01L23/498 ,  H01L23/34

CPC classification number: H01L21/4871 ,  H01L21/823487 ,  H01L23/34 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3732 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5226 ,  H01L23/60 ,  H01L25/0657 ,  H01L25/50 ,  H01L27/0207 ,  H01L27/0248 ,  H01L27/0688 ,  H01L27/092 ,  H01L27/098 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2225/06589 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A 3D semiconductor device, including: a first layer including first transistors; a second layer including second transistors; where the second transistors are aligned to the first transistors, and a first circuit including at least one of the first transistors, where the first circuit has a first circuit output connected to at least one of the second transistors, and where at least one of the second transistors is connected to a device output, and where the device output includes a contact port for connection to external devices, and where at least one of the second transistors is substantially larger than at least one of the first transistors.

Abstract translation: 一种3D半导体器件，包括：第一层，包括第一晶体管; 包括第二晶体管的第二层; 其中第二晶体管与第一晶体管对准，以及第一电路，其包括第一晶体管中的至少一个，其中第一电路具有连接到至少一个第二晶体管的第一电路输出，并且其中至少一个 第二晶体管连接到器件输出，并且其中器件输出包括用于连接到外部器件的接触端口，并且其中第二晶体管中的至少一个基本上大于第一晶体管中的至少一个。