公开(公告)号：US09390782B2

公开(公告)日：2016-07-12

申请号：US14306174

申请日：2014-06-16

Applicant: Rambus Inc.

Inventor： Scott C. Best ,  Ely Tsern

IPC: G11C11/406 ,  G06F13/16

CPC classification number: G11C11/406 ,  G06F13/1636 ,  G11C2211/4061

Abstract: An apparatus is disclosed that includes a memory controller chip and memory chips packaged with the memory controller chip. Each memory chip includes normal-retention storage rows that exhibit retention times greater or equal to a first time interval, and having been tested to generate information identifying low-retention storage rows that exhibit retention times less than the first time interval. Refresh logic refreshes the normal-retention storage rows at a first refresh rate corresponding to the first time interval, and refreshes each low-retention storage row at a second refresh rate that is greater than the first refresh rate.

Abstract translation: 公开了一种包括与存储器控制器芯片封装的存储器控​​制器芯片和存储器芯片的装置。 每个存储器芯片包括呈现大于或等于第一时间间隔的保持时间的正常保留存储行，并且已经被测试以生成标识低保留存储行的信息，其表现出小于第一时间间隔的保留时间。 刷新逻辑以对应于第一时间间隔的第一刷新速率刷新正常保留存储行，并且以大于第一刷新率的第二刷新率刷新每个低保留存储行。

公开(公告)号：US20160188911A1

公开(公告)日：2016-06-30

申请号：US14989155

申请日：2016-01-06

Applicant: Rambus Inc.

Inventor： Trung Am Diep ,  Pradeep Batra ,  Brian S. Leibowitz ,  Frederick A. Ware

IPC: G06F21/79 ,  H04L9/30 ,  G06F12/14

CPC classification number: G06F21/79 ,  G06F12/1009 ,  G06F12/1408 ,  G06F2212/1052 ,  G06F2221/2107 ,  H04L9/30

Abstract: A memory controller encrypts contents of a page frame based at least in part on a frame key associated with the page frame. The memory controller generates a first encrypted version of the frame key based at least in part on a first process key associated with a first process, wherein the first encrypted version of the frame key is stored in a first memory table associated with the first process. The memory controller generates a second encrypted version of the frame key based at least in part on a second process key associated with a second process, wherein the second encrypted version of the frame key is stored in a second memory table associated with the second process, the first process and the second process sharing access to the page frame using the first encrypted version of the frame key and the second encrypted version of the frame key, respectively.

Abstract translation: 存储器控制器至少部分地基于与页面帧相关联的帧密钥来加密页面帧的内容。 所述存储器控制器至少部分地基于与第一进程相关联的第一进程密钥来生成所述帧密钥的第一加密版本，其中所述帧密钥的所述第一加密版本被存储在与所述第一进程相关联的第一存储器表中。 所述存储器控制器至少部分地基于与第二进程相关联的第二进程密钥来生成所述帧密钥的第二加密版本，其中所述帧密钥的所述第二加密版本被存储在与所述第二进程相关联的第二存储器表中， 第一进程和第二进程分别使用帧密钥的第一加密版本和帧密钥的第二加密版本共享对页面帧的访问。

公开(公告)号：US20160188498A1

公开(公告)日：2016-06-30

申请号：US14801723

申请日：2015-07-16

Applicant: Rambus Inc.

Inventor： Ian Shaeffer ,  Ely Tsern ,  Craig Hampel

IPC: G06F13/16 ,  G06F13/40

CPC classification number: G11C11/4093 ,  G06F13/16 ,  G06F13/4027 ,  G06F13/4068 ,  G11C5/025 ,  G11C5/04 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/22 ,  G11C7/222 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C11/4096 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/32145 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/14 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device. The buffer device segments and merges the data transferred between the memory controller that expects a particular memory organization and actual memory organization.

公开(公告)号：US20160173128A1

公开(公告)日：2016-06-16

申请号：US14941564

申请日：2015-11-14

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  John Eric Linstadt

IPC: H03M13/05 ,  G06F3/06 ,  H03M13/00 ,  G06F13/16

CPC classification number: H03M13/05 ,  G06F3/0619 ,  G06F3/0653 ,  G06F3/0673 ,  G06F13/1668 ,  H03M13/09 ,  H03M13/1102 ,  H03M13/151 ,  H03M13/1515 ,  H03M13/19

Abstract: Memory controllers, devices and associated methods are disclosed. In one embodiment, a memory controller includes write circuitry to transmit write data to a memory device, the write circuitry includes a write error detection correction (EDC) encoder to generate first error information associated with the write data. Data bus inversion (DBI) circuitry conditionally inverts data bits associated with each of the write data words based on threshold criteria. Read circuitry receives read data from the memory device. The read circuitry includes a read EDC encoder to generate second error information associated with the received read data. Logic evaluates the first and second error information and conditionally reverse-inverts at least a portion of the read data based on the decoding.

Abstract translation: 公开了存储器控制器，设备和相关方法。 在一个实施例中，存储器控制器包括用于将写入数据发送到存储器件的写入电路，写入电路包括写入错误检测校正（EDC）编码器，以产生与写入数据相关联的第一错误信息。 数据总线反相（DBI）电路基于阈值条件有条件地反转与每个写入数据字相关联的数据位。 读取电路从存储器件接收读取数据。 读取电路包括读取EDC编码器以产生与接收到的读取数据相关联的第二错误信息。 逻辑评估第一和第二错误信息，并且基于解码有条件地反转至少一部分读取数据。

公开(公告)号：US20160170924A1

公开(公告)日：2016-06-16

申请号：US15051282

申请日：2016-02-23

Applicant: Rambus Inc.

Inventor： Liji Gopalakrishnan ,  Ian Shaeffer ,  Yi Lu

IPC: G06F13/40 ,  G06F13/16

CPC classification number: G06F13/4068 ,  G06F13/1673 ,  G06F13/1678 ,  G11C5/04 ,  G11C7/1012 ,  G11C7/1039 ,  G11C7/1045 ,  G11C7/1075 ,  G11C11/4093 ,  G11C11/4094 ,  G11C11/4096 ,  Y02D10/14 ,  Y02D10/151

Abstract: A memory device or module selects between alternative command ports. Memory systems with memory modules incorporating such memory devices support point-to-point connectivity and efficient interconnect usage for different numbers of modules. The memory devices and modules can be of programmable data widths. Devices on the same module can be configured select different command ports to facilitate memory threading. Modules can likewise be configured to select different command ports for the same purpose.

Abstract translation: 存储器件或模块在可选命令端口之间进行选择。 具有内存模块的内存系统包含这种内存设备，可支持点对点连接和不同数量模块的高效互连使用。 存储器件和模块可以是可编程数据宽度。 同一模块上的设备可以配置为选择不同的命令端口，以便于内存线程化。 模块同样可以配置为为同一目的选择不同的命令端口。

公开(公告)号：US09368164B2

公开(公告)日：2016-06-14

申请号：US14086818

申请日：2013-11-21

Applicant: RAMBUS INC.

Inventor： Pravin Kumar Venkatesan ,  Kashinath Prabhu ,  Makarand Shirasgaonkar ,  Wayne Dettloff

IPC: G11C7/00 ,  G11C5/14 ,  G11C7/10 ,  G11C7/04 ,  G11C11/4099 ,  G11C29/02 ,  G11C29/04

CPC classification number: G11C29/023 ,  G11C5/147 ,  G11C7/04 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C11/4076 ,  G11C11/4099 ,  G11C29/021 ,  G11C29/028 ,  G11C29/52 ,  G11C2029/0409 ,  G11C2207/2254 ,  H03M1/66

Abstract: A single-ended receiver includes an internal voltage generation circuit to set a first internal reference voltage (Vref). A model voltage generation circuit is configurable to receive an external reference voltage to be calibrated during an initial calibration. The model voltage generation circuit is configurable to track an offset value for voltage-temperature (VT) drift and the offset value is applied to the internal voltage generation circuit to calibrate the internal Vref during a periodic calibration of the single-ended receiver.

Abstract translation: 单端接收器包括用于设定第一内部参考电压（Vref）的内部电压产生电路。 模型电压发生电路可配置为在初始校准期间接收要校准的外部参考电压。 模型电压发生电路可配置为跟踪电压 - 温度（VT）漂移的偏移值，并且在单端接收器的周期性校准期间，将偏移值应用于内部电压产生电路以校准内部Vref。

公开(公告)号：US09355021B2

公开(公告)日：2016-05-31

申请号：US13909339

申请日：2013-06-04

Applicant: Rambus Inc.

Inventor： Frederick A. Ware ,  Kishore Kasamsetty

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/16

CPC classification number: G06F13/4022 ,  G06F3/061 ,  G06F3/0647 ,  G06F3/0683 ,  G06F12/00 ,  G06F12/02 ,  G06F13/1657 ,  G06F13/1668 ,  G06F13/4282 ,  G11C5/02

Abstract: In a data processing system, a buffer integrated-circuit (IC) device includes multiple control interfaces, multiple memory interfaces and switching circuitry to couple each of the control interfaces concurrently to a respective one of the memory interfaces in accordance with a path selection value. A plurality of requestor IC devices are coupled respectively to the control interfaces, and a plurality of memory IC devices are coupled respectively to the memory interfaces.

公开(公告)号：US20160147481A1

公开(公告)日：2016-05-26

申请号：US14787651

申请日：2014-04-25

Applicant: RAMBUS INC.

Inventor： Scott C. Best

IPC: G06F3/06

CPC classification number: G06F3/0656 ,  G06F3/0626 ,  G06F3/0673 ,  G11C5/04 ,  G11C7/1006

Abstract: A buffer circuit (403) includes a primary interface (404), a secondary interface (405), and an encoder/decoder circuit (407A, 407B). The primary interface is configured to communicate on an n-bit channel, wherein n parallel bits on the n-bit channel are coded using data bit inversion (DBI). The secondary interface is configured to communicate with a plurality of integrated circuit devices on a plurality of m-bit channels, each m-bit channel transmitting m parallel bits without using DBI. And the encoder/decoder circuit is configured to translate data words between the n-bit channel of the primary interface and the plurality of m-bit channels of the secondary interface.

Abstract translation: 缓冲电路（403）包括主接口（404），辅助接口（405）和编码器/解码器电路（407A，407B）。 主接口被配置为在n比特信道上通信，其中使用数据比特反转（DBI）对n比特信道上的n个并行比特进行编码。 辅助接口被配置为与多个m位通道上的多个集成电路器件进行通信，每个m位通道在不使用DBI的情况下传输m个并行位。 并且编码器/解码器电路被配置为在主接口的n位信道和辅助接口的多个m位信道之间转换数据字。

公开(公告)号：US09349422B2

公开(公告)日：2016-05-24

申请号：US14687739

申请日：2015-04-15

Applicant: Rambus Inc.

Inventor： Akash Bansal ,  Yohan U. Frans ,  Kishore V. Kasamsetty ,  Todd Bystrom ,  Simon Li ,  Arun Vaidyanath

IPC: G11C7/22 ,  G11C29/02 ,  G06F1/10

CPC classification number: G11C7/22 ,  G06F1/10 ,  G11C7/222 ,  G11C29/023 ,  G11C29/028 ,  G11C2207/2254

Abstract: The disclosed embodiments related to a clocked memory system which performs a calibration operation at a full-rate frequency to determine a full-rate calibration state that specifies a delay between a clock signal and a corresponding data signal in the clocked memory system. Next, the clocked memory system uses the full-rate calibration state to calculate a sub-rate calibration state, which is associated with a sub-rate frequency (e.g., ½, ¼ or ⅛ of the full-rate frequency). The system then uses this sub-rate calibration state when the clocked memory system is operating at the sub-rate frequency. This calculation of the sub-rate state calibration states eliminates the need to perform an additional time-consuming calibration operation for each sub-rate.

Abstract translation: 所公开的实施例涉及一种时钟存储器系统，其以全速率频率执行校准操作，以确定指定时钟信号与时钟控制的存储器系统中的相应数据信号之间的延迟的全速率校准状态。 接下来，时钟存储器系统使用全速率校准状态来计算与子速率频率（例如，全速率频率的1/2，¼或⅛）相关联的子速率校准状态。 当时钟存储器系统以子速率频率工作时，系统然后使用该子速率校准状态。 子速率状态校准状态的这种计算消除了对每个子速率执行附加耗时的校准操作的需要。

公开(公告)号：US20160124895A1

公开(公告)日：2016-05-05

申请号：US14931652

申请日：2015-11-03

Applicant: Rambus Inc.

Inventor： Yohan U. Frans ,  Hae-Chang Lee ,  Brian S. Leibowitz ,  Simon Li ,  Nhat M. Nguyen

IPC: G06F13/42 ,  G06F13/40 ,  G06F13/38

CPC classification number: G06F13/4286 ,  G06F13/385 ,  G06F13/4068 ,  H04L1/0002 ,  H04L1/0015 ,  H04L1/203 ,  H04L1/205 ,  H04L1/243 ,  H04L5/1446 ,  H04L25/0262 ,  H04L25/0292 ,  Y02D50/10

Abstract: A device includes a transmitter coupled to a node, where the node is to couple to a wired link. The transmitter has a plurality of modes of operation including a calibration mode in which a range of communication data rates over the wired link is determined in accordance with a voltage margin corresponding to the wired link at a predetermined error rate. The range of communication data rates includes a maximum data rate, which can be a non-integer multiple of an initial data rate.