公开(公告)号：US11676928B2

公开(公告)日：2023-06-13

申请号：US17396346

申请日：2021-08-06

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Alps) SAS

Inventor： Romain Coffy ,  Patrick Laurent ,  Laurent Schwartz

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/31

CPC classification number: H01L24/24 ,  H01L21/56 ,  H01L23/3185 ,  H01L24/05 ,  H01L24/16 ,  H01L24/73 ,  H01L24/82 ,  H01L2224/0233 ,  H01L2224/02315 ,  H01L2224/02381 ,  H01L2224/16145 ,  H01L2224/24011 ,  H01L2224/24105 ,  H01L2224/24137 ,  H01L2224/24195 ,  H01L2224/24226 ,  H01L2224/73227 ,  H01L2224/73265 ,  H01L2224/73267 ,  H01L2224/82048 ,  H01L2224/82108

Abstract: An integrated circuit chip includes a front face having an electrical connection pad. An overmolded encapsulation block encapsulates the integrated circuit chip and includes a front layer at least partially covering a front face of the integrated circuit chip. A through-hole the encapsulation block is located above the electrical connection pad of the integrated circuit chip. A wall of the through-hole is covered with an inner metal layer that is joined to the front pad of the integrated circuit chip. A front metal layer covers a local zone of the front face of the front layer, with the front metal layer being joined to the inner metal layer to form an electrical connection. The inner metal layer and the front metal layer are attached or anchored to activated additive particles that are included in the material of the encapsulation block.

公开(公告)号：US11675021B2

公开(公告)日：2023-06-13

申请号：US16787358

申请日：2020-02-11

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Jean Camiolo

IPC: G01R31/40 ,  G06F1/26 ,  G06F13/42

CPC classification number: G01R31/40 ,  G06F1/26 ,  G06F13/4282 ,  G06F2213/0026

Abstract: An apparatus is adapted to test a power supply device of the USB-PD type which includes at least one USB Type-C connector. The USB Type-C connector is intended to be connected to the power supply device to be tested. The device is separate from the apparatus.

公开(公告)号：US20230178676A1

公开(公告)日：2023-06-08

申请号：US18075828

申请日：2022-12-06

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Arthur ARNAUD ,  Gabriel MUGNY

IPC: H01L31/107 ,  H01L31/109 ,  H01L31/0352 ,  H01L31/105 ,  H01L27/144

CPC classification number: H01L31/107 ,  H01L31/109 ,  H01L31/035218 ,  H01L31/105 ,  H01L27/1443

Abstract: An avalanche photodiode includes a stack of layers. The stack of layers includes an avalanche diode (of PN or PIN type) and a layer having quantum dots located therein. The stack of layers further includes: a charge extraction layer over the layer which includes quantum dots; a transparent conducting layer over the charge extraction layer; and an insulating layer over the transparent conducting layer. The quantum dots includes ligands formed by molecules of dopants.

公开(公告)号：US20230176093A1

公开(公告)日：2023-06-08

申请号：US18053974

申请日：2022-11-09

Applicant: STMicroelectronics (Grenoble 2) SAS

Inventor： Christophe Lorin

IPC: G01R15/14 ,  G01R1/20 ,  G01R27/14

CPC classification number: G01R15/146 ,  G01R1/203 ,  G01R27/14

Abstract: In accordance with an embodiment, an integrated circuit chip includes a first input configured to receive a rectified potential and a second input configured to receive a reference potential; a first circuit configured to maintain the rectified potential at a constant value on the first input; a second circuit having a power supply input coupled to the first node; a first resistor series-connected to the first circuit between the second input and the first node, or connected between the first input and the first node; a third circuit connected across the first resistor and configured to deliver a signal which is an image of a current in the first resistor; and a fourth circuit configured to determine a mains frequency and/or a mains voltage based at least on the signal which is the image of the current in the first resistor.

公开(公告)号：US20230163754A1

公开(公告)日：2023-05-25

申请号：US18056153

申请日：2022-11-16

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS (ROUSSET) SAS

Inventor： Ugo MUREDDU ,  Gilles PELISSIER ,  Guillaume REYMOND

IPC: H03K5/133 ,  H03K5/156

CPC classification number: H03K5/133 ,  H03K5/1565 ,  G11C8/18

Abstract: A wobulated signal generator includes a chain of delay elements and control circuitry. The chain of delay elements includes first delay elements, second delay elements, and third delay elements. The control circuitry, in operation, enables a number of the first delay elements, disables a number of the third delay elements, and enables a selected number of the second delay elements, defining a period of time between two consecutive rising edges of a digital wobulated signal at an output of the wobulated signal generator. The control circuitry monitors an average frequency of the digitally wobulated signal, and selectively modifies the number of enabled first delay elements and the number of disabled third delay elements based on the monitored average frequency of the digitally wobulated signal.

公开(公告)号：US20230161646A1

公开(公告)日：2023-05-25

申请号：US18058648

申请日：2022-11-23

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Isabelle Carnel ,  Valerie Assemat ,  Edwin Hilkens ,  Jeremy Ribeiro De Freitas ,  Jean Claude Bini

IPC: G06F9/54 ,  G06F9/48

CPC classification number: G06F9/542 ,  G06F9/4881

Abstract: In an embodiment an integrated circuit includes a digital-signal processing unit having an event management device configured to associate respective event data items with respective trigger signals and a digital-signal processor configured to associate a respective task with an respective event data item, wherein the event management device is configured to receive the trigger signals at input terminals and, when a trigger signal is received, store the event data item associated with the received trigger signal in an event register, and wherein the digital-signal processor is configured execute the task associated with the event data item stored in the event register.

公开(公告)号：US20230152126A1

公开(公告)日：2023-05-18

申请号：US18155531

申请日：2023-01-17

Applicant: STMicroelectronics (Rousset) SAS ,  STMicroelectronics SA ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Laurent Beyly ,  Oliver Richard ,  Kenichi OKU

IPC: G01D5/24 ,  H03K17/96

CPC classification number: G01D5/24 ,  H03K17/962 ,  H03K2217/9607

Abstract: An embodiment of the present disclosure relates to a method of detection of a touch contact by a sensor including a first step of comparison of a voltage with a first voltage threshold; and a second step of comparison of the voltage with a second voltage threshold, the second step being implemented if the first voltage threshold has been reached within a duration shorter than a first duration threshold, the second voltage threshold being higher than the first voltage threshold.

公开(公告)号：US11653582B2

公开(公告)日：2023-05-16

申请号：US16184246

申请日：2018-11-08

Applicant: STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Franck Arnaud ,  David Galpin ,  Stephane Zoll ,  Olivier Hinsinger ,  Laurent Favennec ,  Jean-Pierre Oddou ,  Lucile Broussous ,  Philippe Boivin ,  Olivier Weber ,  Philippe Brun ,  Pierre Morin

IPC: H01L45/00 ,  H01L27/24 ,  G11C13/00

CPC classification number: H10N70/8616 ,  G11C13/0004 ,  G11C13/0069 ,  H10B63/30 ,  H10B63/80 ,  H10N70/011 ,  H10N70/021 ,  H10N70/231 ,  H10N70/826 ,  H10N70/8265 ,  H10N70/8413 ,  H10N70/882 ,  G11C2013/008

Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.

公开(公告)号：US20230137239A1

公开(公告)日：2023-05-04

申请号：US17970336

申请日：2022-10-20

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS

Inventor： Younes BOUTALEB ,  David KAIRE ,  Romain COFFY

IPC: H01L23/367 ,  H01L23/373 ,  H01L23/053 ,  H01L21/52

Abstract: The present description concerns an electronic device comprising: an electronic chip comprising an active area on a first surface, and a second surface opposite to the first surface; a substrate, the first surface of said chip being mounted on a third surface of said substrate; and a thermally-conductive cover comprising a transverse portion extending at least above the second surface of said electronic chip, wherein the electronic device further comprises at least one thermally-conductive pillar coupling the second surface of the electronic chip to said transverse portion of said thermally-conductive cover.

公开(公告)号：US20230129973A1

公开(公告)日：2023-04-27

申请号：US17939173

申请日：2022-09-07

Applicant: STMicroelectronics (Alps) SAS ,  STMicroelectronics (Grenoble 2) SAS

Inventor： Reiner Welk ,  Danika Perrin

IPC: H04W52/02 ,  H04W52/52

Abstract: In an embodiment, a radio frequency (RF) receiver circuit includes a main circuit and a wake-up circuit. The main circuit is configured to process RF signals. The wake-up circuit is configured to detect a reception of the RF signals. The wake-up circuit includes an automatic gain control (AGC) loop, and is configured to have a first operating mode where a set point voltage of the loop has a first substantially constant value, and a second operating mode where the set point voltage of the loop has a second value dependent on a power supply voltage of the wake-up circuit.